Riviera-PRO™: OSVVM 2020.08 inclusion, enhanced language support, and new debugging features aim to boost productivity December 08 SemiWiki: Aldec Adds Simulation Acceleration for Microchip FPGAs November 10 Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs November 03 Aldec’s TySOM Family of Embedded System Development Solutions Now Supports Xilinx PYNQ (Python Productivity for Zynq) October 21 Aldec’s TySOM Embedded Development Kits are Now Qualified for AWS IoT Greengrass August 05 View all news
Accelerating Verification Component development with OSVVM Model Independent Transactions Debugging Multi-Core Designs using Vitis + Aldec Riviera-PRO Co-Simulation for Zynq US+ MPSoC Accelerating Large Image and Signal Processing FPGA Design Developments with TySOM-3A-ZU19EG and PYNQ How to Build PCIe Speed Adapters for In-Circuit SoC Emulation High-Performance PCIe 5.0 IP + VIP UVM Verification Environment View all webinars