Riviera-PRO Supports OpenCPI for Heterogeneous Embedded Computing of Mission-Critical Applications June 01 Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected Types March 29 Aldec Suspends all EDA Sales and Distribution Transactions in Russia March 14 Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance January 13 Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries November 16 View all news
Introduction to OpenCPI (US) Jun 30 (Webinar, Online) Introduction to OpenCPI (EU) Jun 30 (Webinar, Online) RISC-V Summit 2022 Jul 20 - 21 (Industry Event, Online) GRCon 22 Sep 26 - 30 (Industry Event, Washington, DC, USA) View all events
Better FPGA Verification with VHDLPart 4: Advances in OSVVM's Verification Data Structures Better FPGA Verification with VHDLPart 3: OSVVM's Test Reports and Simulator Independent Scripting Better FPGA Verification with VHDLPart 2: Faster than Lite Verification Component Development with OSVVM Better FPGA Verification with VHDLPart 1: OSVVM: Leading Edge Verification for the VHDL Community FPGA Design/Verification Best-Practices for Quality and EfficiencyPart 4: Code, Functional and Specification Coverage View all webinars