What’s involved in simulation of a complex SoC FPGA like Versal ACAP? February 08 Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCs June 26 Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs June 14 The avionics industry’s growing need for TLM May 18 Aldec and Thales to Co-Present at Certification Together International Conference 2023 May 01 View all news
VHDL/SystemVerilog RTL verification environment using cocotb ~ Test bench that can be written in Python Nov 20 (Webinar, Tokyo, Japan ) FPGA design verification in a nutshell: Part 1 Nov 27 (Webinar, Tokyo, Japan ) Mastering SoC Design and Verification for DO-254 Compliance – Balancing Complexity and Safety (Hosted by ConsuNova) Jan 23 (Webinar, Online) Simplifying DO-254 Compliance for FPGA Designs – A Practical Approach (EU) Feb 06 (Webinar, Online) Simplifying DO-254 Compliance for FPGA Designs – A Practical Approach (US) Feb 06 (Webinar, Online) View all events
Navigating COTS-IP in DO-254 – Strategies for Safe and Efficient FPGA Design (Hosted by ConsuNova) Static and Dynamic CDC Verification of AXI4 Stream-based IPs The Development and Evolution of Verilog & SystemVerilog Using OSVVM’s AXI4 Verification Components (Part 2) Writing Tests and Configuring the AXI4 VCs Using OSVVM’s AXI4 Verification Components (Part 1) Creating the AXI4 Testbench / Test Harness View all webinars
