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A Proven EDA Solutions Provider makes all the difference.

Our promise to deliver leading verification methodologies that support the latest Ianguage standards allows our customers to grow while leveraging evolving technologies.

FPGA Design

FPGA Vendors Support Simulation and Debugging Project Management Graphical/Text Design Entry Documentation HTML/PDF

Hardware Prototyping

Scalable HES™ Prototyping Platform HES Proto-AXI Interconnect Multi-FPGA Design Partitioning ARM Cortex Support RTAX/RTSX Prototyping

Functional Verification

Metric Driven Verification Universal Verification Methodology (UVM)Open Source VHDL Verification Methodology (OSVVM)Universal VHDL Verification Methodology (UVVM)VUnit Cocotb Static Linting Co-Simulation with QEMU and Riviera-PRO CDC and RDC Verification

FPGA Embedded Solutions

Deep Learning Using Zynq US+ FPGA FPGA-based NVMe Data Storage Internet of Things (IoT)Automotive ADAS Networking Aldec 4K UltraHD Imaging Solutions Python and PYNQ COVID-19 Detection

Hardware Emulation Solutions

SoC Co-emulation UVM Simulation Acceleration Scalability of Acceleration Verification IP SoC Partitioning Emulation Debugging

High Performance Computing

Computer Vision Encryption & Security Genome Alignment High Frequency Trading Large Scale HPC Embedded HPC

DO-254 Compliance

Traceability HDL Coding Standards Tool Assessment and Qualification Process FPGA Level In-Target Testing HDL Detailed Design and Verification DO-254 Templates and Checklists

Specialized Applications

Regression Manager Encryption DSP and RF Co-Simulation

Events

Enforcing HDL coding standards in DO-254 projects Jul 22 (Webinar, Online) Let's try using the constrained random of SystemVerilog Jul 29 (Webinar, Online) Practical Co-Simulation Techniques with OSVVM Part 1: Getting Started with OSVVM Co-Simulation (US) Aug 20 (Webinar, Online) Practical Co-Simulation Techniques with OSVVM Part 1: Getting Started with OSVVM Co-Simulation (EU) Aug 20 (Webinar, Online) Practical Co-Simulation Techniques with OSVVM Part 2: RISC-V Software and Logic Co-Development (EU) Sep 03 (Webinar, Online) View all events

Recorded Webinars

Making a Simple VHDL Testbench Step-by-Step Part 2: BFMs and Simplifications, Demo, and Debugging Making a Simple VHDL Testbench Step-by-Step Part 1: Foundations, Architecture and Basics Design Constraints for CDC Verification: Bridging Timing, Clocks, and Reliable Synchronization VHDL-2019: Just the New Stuff

Part 5: Type System and Language Enhancements Best Practices for Mixed-Language FPGA Design and Verification View all webinars

Newsroom

ALINT-PRO™ Adds New Mixed-Language Design Rules for More Predictable Cross-Language Integration January 14 What’s involved in simulation of a complex SoC FPGA like Versal ACAP? February 08 Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCs June 26 Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs June 14 The avionics industry’s growing need for TLM May 18 View all news

Quicklinks

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