Functional Verification For complex ASIC, FPGA and SoC FPGA designs there are many verification challenges. These include reducing time (to design, simulate and debug) and to achieve an acceptable level of coverage. Aldec’s EDA tools, used in conjunction with industry-standard best practices and popular verification methodologies, help you rise to these challenges and give you confidence in your designs. Metric Driven Verification (MDV) Central to design verification, MDV is the cyclic confirmation that the verification plan and its construction, execution and analysis are working together. It is performed to improve the predictability, productivity, and quality of the verification effort. MDV metrics include code coverage and functional coverage using assertions, SystemVerilog covergroups, and finite state machine (FSM) coverage, all of which are supported by Riviera-PRO and Active-HDL. Also helping you rise to the design verification challenge is the Aldec Coverage DataBase (ACDB), which is our implementation of Accellera UCIS requirements. Verification Methodologies EDA tools for mixed-language simulations must support the latest industry verification methodologies in order to employ various verification strategies and maximize reuse. Both Riviera-PRO and Active-HDL support the following: Open Source VHDL Verification Methodology (OSVVM). This advanced verification methodology defines a VHDL verification framework, verification utility library, verification component library, scripting API, and co-simulation capability that simplifies verification. Using OSVVM it is possible to create a simple, readable, and powerful testbench. Universal Verification Methodology (UVM). Originally created by Accellera in 2011 and standardized in 2020 as IEEE 1800.2-2020, UVM has been the de-facto verification methodology for ASIC designs for at least a decade and is now being used on high-density FPGA and SoC FPGA designs. It is an open- source library written in SystemVerilog, and it utilizes the power of object-oriented programming for hardware designs. Universal VHDL Verification Methodology (UVVM). This is an open source VHDL verification library and methodology, available on both Github and IEEE Standards Association Open, and is developed in cooperation with the European Space Agency (ESA). As with OSVVM, it allows designers to use the language they already know (i.e., VHDL) and add, step-by-step, the functionality needed for their specific testbench. Coroutine cosimulation testbench (cocotb). This is an extremely popular open-source and completely free tool for creating hardware testbenches in Python that can be used to verify designs written in VHDL or Verilog, using your simulator of choice. The VUnit open-source unit testing framework for VHDL and SystemVerilog. VUnit provides the necessary functionality for continuous and automated unit testing of HDL code and complements traditional testing methods by promoting a "test early and often" approach through automation. Design Rule Checking (DRC) Static linting performed using ALINT-PRO on RTL code - written in VHDL, Verilog, or SystemVerilog – ensures HDL code robustness by flagging absolute errors and warnings early on in your design flow. Linting helps detect a wide variety of design issues (including poor coding styles, improper clock and reset management), simulation versus synthesis mismatches, incorrectly implemented finite state machines (FSMs), poor testability, and other typical source code issues throughout the design flow. ALINT-PRO also supports phase-based linting (PBL), which inserts clear priorities into the design analysis process by reducing the total number of issues to be addressed and minimizing the number of design refinement iterations. PBL reduces debugging time by 3 to 10x. Clock/Reset Domain Crossings Clock domain crossing (CDC) and, increasingly, reset domain crossing (RDC) verification is challenging for large, complex designs with multiple clocks and reset lines. ALINT-PRO features an ALDEC_CDC rule plug-in that focuses on clock and reset domain crossings analysis as well as the handling of metastability issues. ALINT-PRO also provides design constraints support, an invaluable aid to verifying metastability, and static and dynamic verification. QEMU Co-Simulation SoC FPGAs, with their processor cores and the ability to run software, present new verification challenges for system, software, and hardware engineers and many HW/SW integration problems are only found on the testbed - i.e., on physical hardware, late in the development lifecycle. Aldec provides a HW/SW co-simulation interface between Riviera-PRO and QEMU, the open-source processor emulator. System integration and co-simulation of HDL code with software applications/drivers executing in QEMU is now simplified with the addition of the Aldec QEMU Bridge, which connects Riviera-PRO and QEMU, and converts SystemC TLM transactions to AXI and vice versa, providing a fast interface for co-simulation. This capability even extends to AMD’s Versal Adaptive Compute Acceleration Platform (ACAP) system-on-chip (SoC) device that builds on the capabilities and performance of the company’s highly successful Zynq 7000 and MPSoC families. The device introduces ‘intelligent engines’ (a combination or AI/ML and signal processing chipsets for functions and workloads that need vector processing, domain-specific parallel processing, and high compute efficiency) and a programmable network on chip (NoC).
