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Name Products Type Action
01 ALINT-PRO Installation   
Learn how to install and run ALINT-PRO
ALINT-PRO Tutorials
01-Creating HDL Text Modules   
Learn how to create HDL Text Modules in Active-HDL
Active-HDL Tutorials
02 ALINT-PRO Workspace and Projects   
Learn how to work with the design structure in ALINT-PRO
ALINT-PRO Tutorials
02-Creating HDL Graphical Modules   
Learn how to create schematic diagram and finite state machine in Active-HDL
Active-HDL Tutorials
03 ALINT-PRO Design Analysis   
Learn how to run design analysis with ALINT-PRO
ALINT-PRO Tutorials
03-Design Flow Manager   
Learn how to use Design Flow Manager in Active-HDL
Active-HDL Tutorials
04 ALINT-PRO Results Analysis   
Learn how to analyze linting results with ALINT-PRO
ALINT-PRO Tutorials
04-Creating Testbenches   
Learn how to create a Testbench in Active-HDL
Active-HDL Tutorials
05 ALINT-PRO RTL Schematic   
Learn how to use the RTL Schematic Viewer in ALINT-PRO
ALINT-PRO Tutorials
05-Running Simulation   
Learn how to run simulation and use waveform viewer in Active-HDL
Active-HDL Tutorials
06 ALINT-PRO Command-line and Batch Mode   
Learn how to use ALINT-PRO in batch mode
ALINT-PRO Tutorials
06-HDL_Debugging   
Learn how to use HDL debugging tools in Active-HDL
Active-HDL Tutorials
07 ALINT-PRO Unit Linting with Active-HDL   
Learn how to run unit linting with ALINT-PRO
ALINT-PRO Tutorials
07-Code_Coverage   
Learn how to use Code Coverage in Active-HDL
Active-HDL Tutorials
08 ALINT-PRO Unit Linting with Riviera-PRO   
Learn how to run ALINT-PRO unit linting within Riviera-PRO framework
ALINT-PRO Tutorials
08-Design_Profiler   
Learn how to use Design Profiler
Active-HDL Tutorials
09-Documentation_Features   
Learn how to export designs to HTML and PDF in Active-HDL
Active-HDL Tutorials
10-Simulink Interface   
Learn how to use Simulink® Interface in Active-HDL
Active-HDL Tutorials
7-Series FPGA Chips Programming on the HES7XV690-4000BP Board    HES-7 Application Notes
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.
HES-DVM White Papers
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614 results (page 1/31)
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