Company Newsroom News Archive News Blog Articles Upcoming Events 2024FEB 08, 2024 What’s involved in simulation of a complex SoC FPGA like Versal ACAP?2023JUN 26, 2023 Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCsJUN 14, 2023 Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP DesignsMAY 18, 2023 The avionics industry’s growing need for TLMMAY 01, 2023 Aldec and Thales to Co-Present at Certification Together International Conference 2023FEB 06, 2023 Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs2022JUN 22, 2022 Verifying at a Higher Level of AbstractionJUN 01, 2022 Riviera-PRO Supports OpenCPI for Heterogeneous Embedded Computing of Mission-Critical ApplicationsMAR 29, 2022 Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected TypesMAR 14, 2022 Aldec Suspends all EDA Sales and Distribution Transactions in RussiaJAN 13, 2022 Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance2021NOV 16, 2021 Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries JUL 19, 2021 New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC DesignsJUL 07, 2021 New TySOM-M Series Targets Low Power, High Security ApplicationsJUN 02, 2021 Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC PrototypingMAY 18, 2021 Riviera-PRO™ Enables VHDL-2019 Users to Unleash the Power of the Language’s New AdditionsMAR 04, 2021 Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-InJAN 20, 2021 Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements2020DEC 08, 2020 Riviera-PRO™: OSVVM 2020.08 inclusion, enhanced language support, and new debugging features aim to boost productivityNOV 10, 2020 SemiWiki: Aldec Adds Simulation Acceleration for Microchip FPGAsNOV 03, 2020 Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA DesignsOCT 21, 2020 Aldec’s TySOM Family of Embedded System Development Solutions Now Supports Xilinx PYNQ (Python Productivity for Zynq) AUG 05, 2020 Aldec’s TySOM Embedded Development Kits are Now Qualified for AWS IoT Greengrass JUL 22, 2020 Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PROJUL 15, 2020 Aldec @ DAC 2020: Presenting RISC-V Verification Methodologies and SolutionsJUN 30, 2020 Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO™ for DO-254 ProjectsJUN 24, 2020 New to Riviera-PRO™: VHDL-2019 Support and a Versatile UVM Registers WindowJUN 22, 2020 Faster FPGA verificationJUN 10, 2020 Webinar Replay – Insight into Creating a Common TestbenchJUN 05, 2020 How To Implement A Real-time Human Detection Application at the Edge Using Zynq UltraScale+ MPSoC DeviceJUN 03, 2020 How to Verify Complex RISC-V–based DesignsMAY 04, 2020 Aldec’s New HES FPGA Accelerator Board Targets HPC, HFT and Prototyping Applications plus Hits the ‘Price/Performance’ Sweet SpotAPR 08, 2020 Complete Traceability Between System and Hardware Lifecycle DataMAR 24, 2020 InterMotion Technology boosts IP verification productivity for Lattice Semiconductor’s CrossLink FPGA family using Aldec’s Active-HDL MAR 02, 2020 Aldec to Present at Certification Together International Conference FEB 19, 2020 Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V CoresJAN 28, 2020 Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec’s Riviera-PRO for HDL Simulation2019DEC 17, 2019 Aldec Enhances Riviera-PRO’s VHDL and UVVM SupportDEC 12, 2019 Aldec’s new FPGA-based NVMe Data Storage Solution Targets High Performance Computing ApplicationsDEC 03, 2019 Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM NOV 26, 2019 Aldec’s Latest Embedded Development Platform is First to Feature Largest PolarFire and SmartFusion2 FPGAs on a Single BoardNOV 26, 2019 Developing Robust Finite State Machines Code With Lint ToolsNOV 18, 2019 Aldec at SC19: Showcasing Multi-FPGA Partitioning Software for Multi-FPGA-based Algorithm AcceleratorsNOV 14, 2019 Aldec Provides the Industry’s Most-Comprehensive Portfolio of FMC Daughter CardsOCT 21, 2019 Aldec at DVCon Europe: Demonstrating a hybrid co-verification platform for ASIC/SoC projects and automated FPGA partitioning softwareOCT 02, 2019 Aldec’s Focus for Arm TechCon is on Deep Neural Network and Machine Learning Application DevelopmentSEP 24, 2019 Aldec cuts ASIC design prototype bring-up time with HES-DVM’s automatic partitioning tool and faster HDL-to-FPGA compilation timesSEP 09, 2019 SoC & ASIC designers to benefit greatly from multiple HES Proto-AXI™ enhancementsJUN 18, 2019 Riviera-PRO™ users to benefit from automatic UVM register generation plus the latest verification methodology librariesJUN 03, 2019 Introducing SyntHESer, Aldec’s proprietary high-speed synthesizer for HES emulation and prototypingMAY 15, 2019 Aldec @ DAC 2019: Celebrating its 35th Anniversary and focusing on design acceleration, co-verification and mixed-signalAPR 01, 2019 Hardware Lifecycle Data Management for TeamsFEB 26, 2019 Latest TySOM Kit Accelerates the Development of AI, DNN and Other Algorithm Acceleration-dependent Applications Plus Aids SoC PrototypingJAN 22, 2019 Aldec facilitates design prototyping in FPGA and prototype testing with new HES Proto-AXIJAN 14, 2019 Aldec shortens time of ASIC design prototype bring-up in FPGA with HES-DVM Proto mode2018NOV 13, 2018 VHDL 2018 Support & Enhanced Automation - Aldec adds VHDL Standard 1076-2018 extensions and automatic coverage model generation to Riviera-PRO™OCT 22, 2018 Aldec’s “Hardware and Software Co-verification in Hybrid Simulation and Emulation Environment with QEMU” DVCon Europe tutorial to demonstrate how engineers can obtain a holistic view over their SoC designOCT 15, 2018 A View from AboveOCT 15, 2018 Visible BenefitsAUG 08, 2018 SemiWiki: Enhancing Early Static FSMJUL 20, 2018 Aldec to Present at the 6th China National FPGA Industry Development ForumJUL 19, 2018 Enhanced early static checks of Finite State Machines and Xilinx IP-based designsJUN 11, 2018 SemiWiki: RAL, Lint and VHDL-2018JUN 07, 2018 Aldec @ DAC 2018: Presenting Innovative SoC Design & Verification MethodologiesMAY 08, 2018 Three Enhancements in One - Aldec bolsters Riviera-PRO™ with automatic UVM register generation, Unit Linting and the ability to handle early VHDL 2018 extensionsMAY 02, 2018 Aldec and Tamba Networks Release Ultra Low Latency Ethernet Solution for UltraScale+ FPGA at The Trading Show 2018APR 18, 2018 SemiWiki: RDC - A Cousin To CDCAPR 11, 2018 Aldec’s HES UltraScale+ Reconfigurable Accelerator and Northwest Logic’s PCI Express Cores Provide Proven PCI Express SolutionMAR 12, 2018 SemiWiki: Clock Domain Crossing in FPGAFEB 21, 2018 Aldec to showcase Verification Spectrum for SoC FPGAs at Embedded World 2018FEB 20, 2018 QuickLogic Announces Partnership with Aldec for eFPGA Simulation FlowFEB 08, 2018 Aldec presents ‘Dealing with CDC verification complexity in large-scale FPGA designs’ at FPGA Forum 2018FEB 07, 2018 Reconfigurable high-performance routers and switches - made easyFEB 05, 2018 Engineering Productivity Improved through Early Code Quality Checks JAN 30, 2018 SemiWiki: Conflating ISO 26262 and DO-254JAN 17, 2018 Assure robustness of Finite State Machines and Reset Domain Crossings – via early static checks 2017DEC 21, 2017 Aldec and High-Performance ComputingDEC 13, 2017 Aldec releases re-configurable FPGA-based accelerators for High Frequency Trading applicationsNOV 15, 2017 Hardware and software engineers designing SoC FPGAs stand to profit from Aldec QEMU BridgeNOV 15, 2017 Living on the EdgeNOV 09, 2017 Aldec to showcase FPGA-based algorithm accelerators at SC17OCT 23, 2017 Aldec unveils Zynq™ MPSoC ZU7EV Embedded Board at ARM TechCon 2017OCT 10, 2017 SemiWiki: An IIot Gateway to the CloudOCT 09, 2017 Aldec to Present Software Driven Test of FPGA Prototype @ DVCon Europe 2017 SEP 19, 2017 SemiWiki: Partitioning for PrototypesSEP 17, 2017 Aldec presents 'HDL Coding Standards and Best Practices for DO-254’ tutorial at the 36th Annual DASC SEP 12, 2017 Aldec @ DVCon India 2017 - accelerating SoC validation by extending QEMU open-source capabilitiesSEP 11, 2017 Aldec solves ASIC design partitioning challenges with HES-DVM Proto mode SEP 01, 2017 Intelligent Aerospace: Reprogrammable prototyping solutions: a must for space design verificationAUG 30, 2017 Embedded Vision: Look and IdentifyAUG 08, 2017 Benefit from the power of the latest SystemVerilog subset constructs – with confidence AUG 02, 2017 SemiWiki: Cloud-Based EmulationJUL 03, 2017 SemiWiki: HW and SW Co-verification for Xilinx Zynq SoC FPGAsJUN 15, 2017 Aldec and Silvaco present Mixed-Signal Simulation Solution at DAC 2017JUN 06, 2017 Aldec @ DAC 2017: Presenting Breakthrough Innovations in SoC Design & VerificationJUN 06, 2017 EE Web: The Benefits of HW/SW Co-Simulation for Zynq-Based DesignsMAY 30, 2017 Intelligent Areospace: In safe hands: requirement-based testing for design assurance of complex, safety-critical components with high impacts of failureMAY 29, 2017 SemiWiki Interviews Dr. Stanley Hyduke, founder and CEO of AldecMAY 16, 2017 Aldec to Showcase new Xilinx UltraScale FPGA Accelerator board for High Frequency Trading Applications at The Trading Show 2017 in ChicagoMAY 16, 2017 SemiWiki: High Frequency Trading and EDAMAY 01, 2017 Aldec unveils the newest Xilinx Zynq-based TySOM Embedded Prototyping Board at Embedded Vision Summit 2017APR 26, 2017 A Self-Contained Software-Driven PrototypeAPR 24, 2017 RTL Linting: Proceed with ConfidenceAPR 18, 2017 Q&A with Louie De Luna, Director of Marketing at ALDECAPR 17, 2017 Aldec to Demonstrate Design Verification Techniques with Hardware-In-The-Loop and QEMU at DvCON China 2017APR 11, 2017 Aldec continues to stack up pre-compiled verification libraries and delivers significant SystemVerilog and UVM speedup with latest release of Riviera-PRO APR 07, 2017 Safety AssuredMAR 17, 2017 SemiWiki: Aldec Swings for the FencesMAR 15, 2017 Aldec Celebrates 10 Years in DO-254 at Certification Together International Conference MAR 07, 2017 Aldec Introduces End-to-end HW/SW Co-verification for Xilinx Zynq SoC FPGAs at Embedded World 2017FEB 28, 2017 Aldec unveils Xilinx UltraScale FPGA-based prototyping board enabling Simulation Acceleration and Emulation with the latest release of HES-DVMFEB 23, 2017 Aldec to Demonstrate UVM Simulation Acceleration with Network-On-Chip (NoC) Demo Design at DVCon U.S. 2017FEB 23, 2017 Better Code With RTL Linting And CDC VerificationFEB 21, 2017 Aldec to Showcase FPGA Acceleration of Genome Alignment, Motion Detection and Face Detection Algorithms at isFPGA 2017FEB 16, 2017 Aldec Rounds Out ALINT-PRO CheckerFEB 14, 2017 Aldec sets a new paradigm with a single platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC designsFEB 01, 2017 Aldec delivers DO-254 Compliant Templates and Checklists with the latest release of Spec-TRACER JAN 19, 2017 Aldec provides Finite State Machine Coverage for verification of safety-critical FPGAs2016DEC 07, 2016 Top Aldec Design and Verification Blog Articles from 2016NOV 16, 2016 Aldec delivers significant SystemVerilog speedup and a pioneering initiative for VHDL users with latest Riviera-PRONOV 14, 2016 Aldec and Indian Institute of Science faculty enterprise, ReneLife, showcase ReneGENE for accurate genome alignment on HES Accelerator at SC16NOV 14, 2016 SemiWiki: 3 in 1 Hardware VerificationNOV 10, 2016 Aldec adds largest Xilinx UltraScale to latest HES Solution for FPGA Simulation Acceleration, Emulation, and Prototyping to be unveiled at SemIsrael 2016 OCT 27, 2016 Semiconductor Engineering: Emulation’s Footprint GrowsOCT 27, 2016 Semiconductor Engineering: Too Big To Simulate?OCT 24, 2016 SemiWiki: FPGAs for a few thousand devices moreOCT 20, 2016 Aldec to Showcase Xilinx Zynq-based ADAS and IoT Gateway Development Platforms at ARM TechCon 2016 OCT 11, 2016 Aldec to Highlight ASIC Pre-Silicon Verification Spectrum with Network-On-Chip (NoC) Demonstration at DVCon EuropeSEP 19, 2016 SemiWiki: Up front phases improve CDC analysisSEP 05, 2016 Intelligent Aerospace: FPGA verification techniques for avionics applicationsAUG 17, 2016 SemiWiki: Optimization and verification wins in IoT designsAUG 16, 2016 Aldec Delivers Verification Support for Embedded Applications with New Xilinx Zynq-based TySOM Embedded Development Kit AUG 15, 2016 Embedded Computing Design: Verification is crucial for programmable SoC designsJUL 12, 2016 Aldec Increases Verification Productivity with the latest release of Riviera-PROMAY 24, 2016 Aldec @ DAC 2016: Scalable Emulation, Prototyping, IoT, ASIC Verification Spectrum and MoreMAY 17, 2016 Aldec Extends Spectrum of Verification Tools for Use in Digital ASIC DesignsMAR 16, 2016 Aldec to Offer Complete Coverage Analysis with the Addition of Condition and Path Coverage to Active-HDL’s Powerful Coverage DatabaseMAR 15, 2016 Aldec Introduces SCE-MI Pipes-based Flow for Streaming High-volume Data and 30% Speed Increase with Latest Release of HES-DVM MAR 11, 2016 Design units come to faster Riviera-PRO releaseMAR 09, 2016 Aldec delivers enhanced UVM Support and New Debugging Features with the latest release of Riviera-PROFEB 26, 2016 Aldec reprograms HES7 for AXI4 speedFEB 24, 2016 Aldec to unveil HES-7 High-speed AXI Transmission Channel at DVCon 2016FEB 03, 2016 Updated tool cuts through DO-254 V&V chaosFEB 02, 2016 Aldec Streamlines Management of DO-254 Validation and Verification with Spec-TRACER™ FEB 02, 2016 FirstEDA to introduce Aldec’s FPGA Co-emulator at Verification Futures Europe2015DEC 21, 2015 Helpful Aldec Design and Verification Blog Articles from 2015DEC 15, 2015 Push the UVM start button then hit the accelerator, Part 2NOV 10, 2015 Push the UVM Start Button then Hit the AcceleratorNOV 04, 2015 DVCon Europe “must see”: Aldec tutorial and demonstration on adopting Easier UVM to enable FPGA-based AccelerationOCT 29, 2015 Say Hi To Hybrid: ARM Fast Models meet Aldec EmulationOCT 29, 2015 Aldec HES™ Co-emulation named a finalist in this year’s ARM® TechCon Innovation ChallengeOCT 27, 2015 Aldec Introduces Hybrid Emulation with ARM® Fast Model SupportOCT 20, 2015 50+ Successful DO-254 Projects Supported by Aldec’s FPGA Test System; Now with Pre-Tool Qualification Data PackageAUG 31, 2015 EE Times: Hybrid Emulation: It's about time!AUG 10, 2015 Aldec enhances ALINT-PRO-CDC with Advanced Violation Analysis Capabilities and an Extended Set of Dynamic Checks JUL 30, 2015 Aldec delivers complete Coverage Analysis for FPGA and ASIC Designers with the latest release of Riviera-PROJUL 06, 2015 Aldec to offer DAC Technical Sessions Live OnlineJUL 02, 2015 Semiconductor Engineering: UVM: What’s Stopping You?JUN 01, 2015 Concept Engineering′s Nlview™ Schematic Visualization Engine to Power Aldec′s ALINT-PRO-CDC™ CDC Verification Solution JUN 01, 2015 SemiWiki: Aldec packs 6 UltraScale parts on HES-7MAY 28, 2015 Scale & Scalability -- The Keys to True FPGA-Based VerificationMAY 27, 2015 Aldec HES-7 with Xilinx Virtex UltraScale Devices Enables True FPGA-based VerificationMAY 26, 2015 Aldec @ DAC 2015: Scalable Prototyping, UVM Simulation, Productivity Gains using Python and MoreMAY 13, 2015 Chip Design: CDC Verification: Using Both Static and Dynamic Checking is Key to SuccessMAY 13, 2015 Embedded Computing Design: You needn't decide between prototype or emulationMAY 04, 2015 Xilinx Accelerates System Verification with Vivado Design Suite 2015.1MAR 10, 2015 Aldec Delivers Support for Test Ranking in Code Coverage AnalysisFEB 18, 2015 Aldec to deliver DO-254 Hardware Testing Presentation at Certification Together Intl. Conference (CTIC)FEB 09, 2015 Aldec Announces HES-7, the Largest Off-The-Shelf Xilinx Virtex-7 FPGA Prototyping System at up to 288 Million ASIC Gates CapacityJAN 29, 2015 Aldec launches ALINT-PRO-CDC™ delivering comprehensive CDC Verification Strategies for SoC and FPGA Designs JAN 19, 2015 Aldec Increasing the Return on SimulationJAN 15, 2015 Aldec Delivers Unprecedented Scalability and Verification Acceleration with the Latest Release of HES-DVM™2014DEC 23, 2014 Embedded Computing Design: Top five reasons why you need Requirements TraceabilityDEC 10, 2014 Aldec extends DOORS® Traceability to FPGA/SoC designs with Spec-TRACER™DEC 08, 2014 Aldec Releases Active-HDL 10.1 with 64-bit simulation supportNOV 29, 2014 Verification Plans Overcome Hope-Based CoverageNOV 12, 2014 Aldec Delivers Efficient Verification with Requirements-based, User-defined Test Plan in CoverageOCT 25, 2014 3 Reasons to Focus on Hardware Dependent Software OCT 07, 2014 Putting the ‘A’ in EDAOCT 02, 2014 Aldec and FTD Solutions Ink Distribution Agreement for Southeast AsiaSEP 29, 2014 Aldec Serves up Emulation and Static Design Rule Check Solutions at 10th annual ARM TechCon ConferenceSEP 26, 2014 Dominating FPGA Clock Domains and CDCs SEP 23, 2014 Aldec Distributor, Prodigy Technovations, to Showcase Aldec Advanced Verification Platforms at DVCon IndiaSEP 08, 2014 Aldec to Demonstrate Support for Xilinx UltraSCALE and SoC at X-Fest Events in North America AUG 14, 2014 Announcement: Riviera-PRO EDU Available on EDA PlaygroundAUG 05, 2014 Aldec delivers Rapid Debugging with UVM Toolbox™ to Interpret Complex UVM Verification EnvironmentsJUL 31, 2014 Semiwiki: Then, Python walked in for verificationJUN 26, 2014 Semiwiki: Real FPGAs don’t eat fake test vectorsJUN 23, 2014 Aldec to offer ‘DAC CHAT’ Technical Sessions Live OnlineJUN 17, 2014 Semiwiki: Aldec Can Ensure Smooth System Integration JUN 16, 2014 Elbit Systems deploys Aldec DO-254/CTS and Passes EASA Verification Audit for Level A SystemMAY 30, 2014 Why Aldec’s Long-Term VP, Dave Rinehart, Is No Longer with The Company?MAY 02, 2014 Semiwiki: Aldec is Celebrating 30 Years @ #51DAC!APR 30, 2014 Aldec Celebrates 30 Years in EDA: Presenting Advanced Verification and Emulation Solutions at DAC 2014APR 22, 2014 Semiwiki: Learning an HDL SimulatorAPR 22, 2014 Semiwiki: You didn’t say it has to workMAR 19, 2014 Semiwiki: Aldec the leader in DO254MAR 11, 2014 Semiwiki: Now even I can spot bad UVM MAR 05, 2014 Aldec Presents a Visual Mapping Solution to Capture a Bird’s-eye View of UVM Verification Environments FEB 28, 2014 Semiwiki: Locked on FPGA design brand recognitionJAN 28, 2014 Aldec solves another DO-254 challenge with Requirements Reviewer in Spec-TRACER™JAN 16, 2014 Top Aldec.com White Paper Downloads from 2013JAN 06, 2014 Top 10 Aldec Design and Verification Blog Articles from 20132013DEC 19, 2013 Celebrate The Season All Over the World with AldecDEC 10, 2013 Oki Information Systems® Leverages Aldec® Advanced Verification Solutions for Xilinx® FPGA Design NOV 25, 2013 NEC Corporation Adopts Aldec® ALINT™ for Communication Systems LSI DesignNOV 12, 2013 Aldec Offers a Visual Approach to Debugging X-Issues in SimulationNOV 04, 2013 SemiWiki: I could show you the FPGA, but then I’d have to configure youOCT 23, 2013 Aldec delivers Global Project Management for Complex FPGA Designs with the latest release of Active-HDL™SEP 23, 2013 Aldec HES-7 SoC Prototyping Solution Adopted by Kumamoto University in JapanAUG 26, 2013 Aldec’s Active-HDL Celebrates Sweet 16 with Another Top FPGA Design AwardJUL 31, 2013 Aldec and NEC Corp. Ink Distributorship Agreement for CyberWorkBench® ASIC/FPGA High Level Synthesis Solution JUL 11, 2013 Aldec Verifies Compatibility of Northwest Logic’s PCI Express Cores with HES-7™ SoC/ASIC Prototyping PlatformJUL 10, 2013 Aldec Enables Class Hierarchy Visualization for UVM-Based Verification EnvironmentsJUN 11, 2013 Missed DAC? Aldec to offer Technical Sessions OnlineMAY 20, 2013 Aldec launches Spec-TRACER™ – Requirements Lifecycle Management for Safety-critical FPGA and ASIC DesignsMAY 15, 2013 Aldec @ DAC 2013: Advanced Verification, HW/SW Emulation, SoC/ASIC Prototyping and moreAPR 29, 2013 Aldec Israel to Showcase Innovative Functional Verification Solutions at ChipEx2013 in Tel AvivAPR 08, 2013 Aldec Presents at Military & Aerospace Programmable Logic Devices Symposium (MAPLD)APR 04, 2013 DSP Survey, Solutions and ResourcesMAR 28, 2013 The latest in SoC and ASIC Prototyping News, Events and ResourcesMAR 21, 2013 New Electronics: ASIC/SoC Prototyping Platforms Increase ProductivityMAR 21, 2013 Semiwiki: Plotting to take over the time-domain only worldMAR 11, 2013 Aldec Releases Plot Window to Increase Productivity of Traditional Waveform-Based HDL DebuggingMAR 08, 2013 EDA Café interviews Aldec Director of Sales, Keith McCann, at DVCon 2013FEB 27, 2013 The latest in ASIC Prototyping News, Events and ResourcesFEB 26, 2013 Aldec offers Advanced Screening of Functional Verification Platform’s Latest Release at DVCon 2013FEB 25, 2013 Aldec Adds Assertions Training to Fast Track Online ProgramFEB 04, 2013 Aldec Launches Free Online UVM TrainingJAN 29, 2013 Follow Aldec. Win a Kindle Fire HD. JAN 07, 2013 Hitachi Cable, Ltd. Deploys ALINT™ on Next Generation FPGA DesignJAN 02, 2013 Aldec Emulation and Verification Tools Adopted by Taiwan National Chiao Tung University for ESL Design Master’s Program2012DEC 20, 2012 Aldec Optimizes FPGA Routing Resources for Power and PerformanceDEC 17, 2012 Now Available - Verification White PapersDEC 12, 2012 EE TIMES: Mil-Aero Top 10 'How-To' articles for 2012, FPGA testing for DO-254 Compliance by AldecDEC 12, 2012 SEMIWIKI: Zynq out of the box, in FPGA-based PrototypingDEC 10, 2012 Aldec Adds ARM Cortex-A9 Support to HES-7 ASIC Prototyping PlatformDEC 04, 2012 "Best of 2012" Top WebinarsDEC 03, 2012 Aldec unwraps SoC/ASIC verification platform at ‘Verification Futures 2012’ in EuropeNOV 14, 2012 Creonic Joins Aldec UNITE™ Partner Programme and Accelerates the Development of its IP Cores with Aldec Linting and Advanced Verification ToolsNOV 05, 2012 Aldec Boosts VHDL Simulation PerformanceNOV 05, 2012 Aldec gives SoC Software Engineers early access to Hardware Aldec Inc. presents on Platform Validation at Verification Futures 2012OCT 29, 2012 EE Journal Chalk Talk “Integrated Design Environment for FPGA” With Aldec Product Manager, Satyam JaniSEP 24, 2012 Aldec Enhances Award-Winning Active-HDL with Flexible File Management to Manage Complex FPGA ProjectsSEP 17, 2012 Aldec Enters ASIC Prototyping Market with HES-7™ Leveraging Xilinx’s Virtex®-7, HES-7 expands up to 96m ASIC Gate CapacityAUG 15, 2012 SOC Central: Verific Design Automation's SystemVerilog, VHDL Parsers Linked with Aldec's Hardware Emulation SolutionJUL 18, 2012 Q3-2012 - Aldec™ Design and Verification NewsletterJUL 17, 2012 TVS Validates UVM based VIP with Aldec’s Riviera-PRO PlatformJUL 10, 2012 Aldec and Agilent Technologies Bridge the Gap Between ESL and RTL by Linking Simulation EnvironmentsJUL 03, 2012 Aldec invited to present "FPGA Level In-Target Testing for DO-254 Compliance" at Avionics Conference in South KoreaJUN 13, 2012 EDACafe: Aldec Update with Al the Robot and App. Engineering Director, Igor TsapenkoJUN 12, 2012 DAC 2012 Wrap UpJUN 06, 2012 EE Times: FPGA-based SoC Verification ChallengesJUN 06, 2012 Tech Design Forum: Where there’s a will… there’s a way to better VHDL verificationMAY 31, 2012 Open-Source VHDL Verification Methodology (OS-VVM) User Group to unveil Advanced Test Methodologies for VHDL Designers at DACMAY 23, 2012 Aldec at DAC 2012: 10 Face-to-Face SessionsMAY 22, 2012 EE Times: FPGA Testing for DO-254 ComplianceMAY 22, 2012 Sigasi integrates Aldec Simulator to Accelerate Feedback CycleMAY 21, 2012 Tanner EDA and Aldec Deliver High-performance A/MS Solution for Mixed-signal IC Design and VerificationMAY 09, 2012 Verified: the need for continued VHDL supportMAY 08, 2012 EE Journal: Aldec Harnesses Massive Server CapacityMAY 01, 2012 Aldec Israel to Serve Up the Latest in Functional Verification at ChipEx2012 in Tel AvivAPR 18, 2012 Aldec Solutions Support Hardware Architecture of Zynq EPP at X-Fest 2012APR 12, 2012 Q2-2012 - Aldec™ Design and Verification NewsletterAPR 11, 2012 EE Times: Automatic C-to-VHDL Testbench Generation Shortens FPGA Development TimeMAR 20, 2012 EDA Café: Testing Made Easy: Open Source VHDL Verification MethodologyMAR 13, 2012 Electronics Weekly: FPGA Verification for DO-254 is in the HardwareMAR 12, 2012 Aldec Takes FPGA & ASIC Debugging to the Next LevelMAR 12, 2012 Electronics Weekly: Aldec Design Tool Supports UVM and new SystemVerilogFEB 29, 2012 Aldec Launches DO-254 Practitioner’s Course with FAA DER, Randall FultonFEB 20, 2012 Aldec to Address Biggest Safety and Mission-Critical Verification Challenges in Electronic Warfare at EWCI in IndiaJAN 23, 2012 Aldec adds Documentation for Safety-Critical Designs in ALINT™ 2012.01JAN 19, 2012 Q1-2012 - Aldec™ Design and Verification NewsletterJAN 13, 2012 Verification Engineers are Invited to Take a Brief Survey and Receive a Chance to win an Ipad2!JAN 09, 2012 Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM™2011NOV 14, 2011 Aldec Delivers Complete Support for UVM 1.1, Enabling VMM and OVM InteroperabilityOCT 31, 2011 Aldec Releases Active-HDL 9.1 Supporting Simulation of the Newest FPGA DevicesOCT 18, 2011 Aldec presents ‘Automated Code Reviews for Fail-Safe Designs’ at ReSpace/MAPLD 2011 Conference in Albuquerque, NM.OCT 18, 2011 Aldec presents 'FPGA Level In-Hardware Verification for DO-254 Compliance' at the 30th Annual DASC in WashingtonOCT 16, 2011 IEEE: FPGA Level In-Hardware Verification for DO-254 ComplianceOCT 06, 2011 Aldec Confirms Platinum Sponsorship of 9th Annual International System-on-Chip (SoC) ConferenceOCT 06, 2011 Q4-2011 - Aldec™ Design and Verification NewsletterSEP 14, 2011 Aldec Honored for Superior FPGA Design and Verification toolsSEP 13, 2011 Aldec and Agnisys Partner to offer Closed Loop Verification Management to meet challenges in Verification of Modern DesignsSEP 12, 2011 Randall Fulton, FAA Consultant DER, to present DO-254 Training Seminar hosted by Aldec in Las Vegas, NVAUG 03, 2011 Functional Verification Survey WinnersJUL 25, 2011 Aldec’s Emulation and Verification Tools Adopted by UC San Diego for the new Master’s Program in Wireless Embedded SystemsJUL 21, 2011 Q3-2011 - Aldec™ Design and Verification NewsletterJUL 11, 2011 Aldec Adds UVM Transaction-Level Visual DebuggingJUL 07, 2011 Design your own Functional Verification ToolJAN 13, 2011 Q1-2011 - Aldec™ Design and Verification Newsletter2008SEP 22, 2008 Aldec selected by Thales to deploy DO-254/ED-80 CTS for Level B Certification Compliance of Advanced Avionics System
