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News Archive

2024
- FEB 08, 2024
  What’s involved in simulation of a complex SoC FPGA like Versal ACAP?
2023
- JUN 26, 2023
  Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCs
- JUN 14, 2023
  Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs
- MAY 18, 2023
  The avionics industry’s growing need for TLM
- MAY 01, 2023
  Aldec and Thales to Co-Present at Certification Together International Conference 2023
- FEB 06, 2023
  Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs
2022
2021
2020
2019
2018
2017
- DEC 21, 2017
  Aldec and High-Performance Computing
- DEC 13, 2017
  Aldec releases re-configurable FPGA-based accelerators for High Frequency Trading applications
- NOV 15, 2017
  Hardware and software engineers designing SoC FPGAs stand to profit from Aldec QEMU Bridge
- NOV 15, 2017
  Living on the Edge
- NOV 09, 2017
  Aldec to showcase FPGA-based algorithm accelerators at SC17
- OCT 23, 2017
  Aldec unveils Zynq™ MPSoC ZU7EV Embedded Board at ARM TechCon 2017
- OCT 10, 2017
  SemiWiki: An IIot Gateway to the Cloud
- OCT 09, 2017
  Aldec to Present Software Driven Test of FPGA Prototype @ DVCon Europe 2017
- SEP 19, 2017
  SemiWiki: Partitioning for Prototypes
- SEP 17, 2017
  Aldec presents 'HDL Coding Standards and Best Practices for DO-254’ tutorial at the 36th Annual DASC
- SEP 12, 2017
  Aldec @ DVCon India 2017 - accelerating SoC validation by extending QEMU open-source capabilities
- SEP 11, 2017
  Aldec solves ASIC design partitioning challenges with HES-DVM Proto mode
- SEP 01, 2017
  Intelligent Aerospace: Reprogrammable prototyping solutions: a must for space design verification
- AUG 30, 2017
  Embedded Vision: Look and Identify
- AUG 08, 2017
  Benefit from the power of the latest SystemVerilog subset constructs – with confidence
- AUG 02, 2017
  SemiWiki: Cloud-Based Emulation
- JUL 03, 2017
  SemiWiki: HW and SW Co-verification for Xilinx Zynq SoC FPGAs
- JUN 15, 2017
  Aldec and Silvaco present Mixed-Signal Simulation Solution at DAC 2017
- JUN 06, 2017
  Aldec @ DAC 2017: Presenting Breakthrough Innovations in SoC Design & Verification
- JUN 06, 2017
  EE Web: The Benefits of HW/SW Co-Simulation for Zynq-Based Designs
- MAY 30, 2017
  Intelligent Areospace: In safe hands: requirement-based testing for design assurance of complex, safety-critical components with high impacts of failure
- MAY 29, 2017
  SemiWiki Interviews Dr. Stanley Hyduke, founder and CEO of Aldec
- MAY 16, 2017
  Aldec to Showcase new Xilinx UltraScale FPGA Accelerator board for High Frequency Trading Applications at The Trading Show 2017 in Chicago
- MAY 16, 2017
  SemiWiki: High Frequency Trading and EDA
- MAY 01, 2017
  Aldec unveils the newest Xilinx Zynq-based TySOM Embedded Prototyping Board at Embedded Vision Summit 2017
- APR 26, 2017
  A Self-Contained Software-Driven Prototype
- APR 24, 2017
  RTL Linting: Proceed with Confidence
- APR 18, 2017
  Q&A with Louie De Luna, Director of Marketing at ALDEC
- APR 17, 2017
  Aldec to Demonstrate Design Verification Techniques with Hardware-In-The-Loop and QEMU at DvCON China 2017
- APR 11, 2017
  Aldec continues to stack up pre-compiled verification libraries and delivers significant SystemVerilog and UVM speedup with latest release of Riviera-PRO
- APR 07, 2017
  Safety Assured
- MAR 17, 2017
  SemiWiki: Aldec Swings for the Fences
- MAR 15, 2017
  Aldec Celebrates 10 Years in DO-254 at Certification Together International Conference
- MAR 07, 2017
  Aldec Introduces End-to-end HW/SW Co-verification for Xilinx Zynq SoC FPGAs at Embedded World 2017
- FEB 28, 2017
  Aldec unveils Xilinx UltraScale FPGA-based prototyping board enabling Simulation Acceleration and Emulation with the latest release of HES-DVM
- FEB 23, 2017
  Aldec to Demonstrate UVM Simulation Acceleration with Network-On-Chip (NoC) Demo Design at DVCon U.S. 2017
- FEB 23, 2017
  Better Code With RTL Linting And CDC Verification
- FEB 21, 2017
  Aldec to Showcase FPGA Acceleration of Genome Alignment, Motion Detection and Face Detection Algorithms at isFPGA 2017
- FEB 16, 2017
  Aldec Rounds Out ALINT-PRO Checker
- FEB 14, 2017
  Aldec sets a new paradigm with a single platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC designs
- FEB 01, 2017
  Aldec delivers DO-254 Compliant Templates and Checklists with the latest release of Spec-TRACER
- JAN 19, 2017
  Aldec provides Finite State Machine Coverage for verification of safety-critical FPGAs
2016
2015
2014
- DEC 23, 2014
  Embedded Computing Design: Top five reasons why you need Requirements Traceability
- DEC 10, 2014
  Aldec extends DOORS® Traceability to FPGA/SoC designs with Spec-TRACER™
- DEC 08, 2014
  Aldec Releases Active-HDL 10.1 with 64-bit simulation support
- NOV 29, 2014
  Verification Plans Overcome Hope-Based Coverage
- NOV 12, 2014
  Aldec Delivers Efficient Verification with Requirements-based, User-defined Test Plan in Coverage
- OCT 25, 2014
  3 Reasons to Focus on Hardware Dependent Software
- OCT 07, 2014
  Putting the ‘A’ in EDA
- OCT 02, 2014
  Aldec and FTD Solutions Ink Distribution Agreement for Southeast Asia
- SEP 29, 2014
  Aldec Serves up Emulation and Static Design Rule Check Solutions at 10th annual ARM TechCon Conference
- SEP 26, 2014
  Dominating FPGA Clock Domains and CDCs
- SEP 23, 2014
  Aldec Distributor, Prodigy Technovations, to Showcase Aldec Advanced Verification Platforms at DVCon India
- SEP 08, 2014
  Aldec to Demonstrate Support for Xilinx UltraSCALE and SoC at X-Fest Events in North America
- AUG 14, 2014
  Announcement: Riviera-PRO EDU Available on EDA Playground
- AUG 05, 2014
  Aldec delivers Rapid Debugging with UVM Toolbox™ to Interpret Complex UVM Verification Environments
- JUL 31, 2014
  Semiwiki: Then, Python walked in for verification
- JUN 26, 2014
  Semiwiki: Real FPGAs don’t eat fake test vectors
- JUN 23, 2014
  Aldec to offer ‘DAC CHAT’ Technical Sessions Live Online
- JUN 17, 2014
  Semiwiki: Aldec Can Ensure Smooth System Integration
- JUN 16, 2014
  Elbit Systems deploys Aldec DO-254/CTS and Passes EASA Verification Audit for Level A System
- MAY 30, 2014
  Why Aldec’s Long-Term VP, Dave Rinehart, Is No Longer with The Company?
- MAY 02, 2014
  Semiwiki: Aldec is Celebrating 30 Years @ #51DAC!
- APR 30, 2014
  Aldec Celebrates 30 Years in EDA: Presenting Advanced Verification and Emulation Solutions at DAC 2014
- APR 22, 2014
  Semiwiki: Learning an HDL Simulator
- APR 22, 2014
  Semiwiki: You didn’t say it has to work
- MAR 19, 2014
  Semiwiki: Aldec the leader in DO254
- MAR 11, 2014
  Semiwiki: Now even I can spot bad UVM
- MAR 05, 2014
  Aldec Presents a Visual Mapping Solution to Capture a Bird’s-eye View of UVM Verification Environments
- FEB 28, 2014
  Semiwiki: Locked on FPGA design brand recognition
- JAN 28, 2014
  Aldec solves another DO-254 challenge with Requirements Reviewer in Spec-TRACER™
- JAN 16, 2014
  Top Aldec.com White Paper Downloads from 2013
- JAN 06, 2014
  Top 10 Aldec Design and Verification Blog Articles from 2013
2013
- DEC 19, 2013
  Celebrate The Season All Over the World with Aldec
- DEC 10, 2013
  Oki Information Systems® Leverages Aldec® Advanced Verification Solutions for Xilinx® FPGA Design
- NOV 25, 2013
  NEC Corporation Adopts Aldec® ALINT™ for Communication Systems LSI Design
- NOV 12, 2013
  Aldec Offers a Visual Approach to Debugging X-Issues in Simulation
- NOV 04, 2013
  SemiWiki: I could show you the FPGA, but then I’d have to configure you
- OCT 23, 2013
  Aldec delivers Global Project Management for Complex FPGA Designs with the latest release of Active-HDL™
- SEP 23, 2013
  Aldec HES-7 SoC Prototyping Solution Adopted by Kumamoto University in Japan
- AUG 26, 2013
  Aldec’s Active-HDL Celebrates Sweet 16 with Another Top FPGA Design Award
- JUL 31, 2013
  Aldec and NEC Corp. Ink Distributorship Agreement for CyberWorkBench® ASIC/FPGA High Level Synthesis Solution
- JUL 11, 2013
  Aldec Verifies Compatibility of Northwest Logic’s PCI Express Cores with HES-7™ SoC/ASIC Prototyping Platform
- JUL 10, 2013
  Aldec Enables Class Hierarchy Visualization for UVM-Based Verification Environments
- JUN 11, 2013
  Missed DAC? Aldec to offer Technical Sessions Online
- MAY 20, 2013
  Aldec launches Spec-TRACER™ – Requirements Lifecycle Management for Safety-critical FPGA and ASIC Designs
- MAY 15, 2013
  Aldec @ DAC 2013: Advanced Verification, HW/SW Emulation, SoC/ASIC Prototyping and more
- APR 29, 2013
  Aldec Israel to Showcase Innovative Functional Verification Solutions at ChipEx2013 in Tel Aviv
- APR 08, 2013
  Aldec Presents at Military & Aerospace Programmable Logic Devices Symposium (MAPLD)
- APR 04, 2013
  DSP Survey, Solutions and Resources
- MAR 28, 2013
  The latest in SoC and ASIC Prototyping News, Events and Resources
- MAR 21, 2013
  New Electronics: ASIC/SoC Prototyping Platforms Increase Productivity
- MAR 21, 2013
  Semiwiki: Plotting to take over the time-domain only world
- MAR 11, 2013
  Aldec Releases Plot Window to Increase Productivity of Traditional Waveform-Based HDL Debugging
- MAR 08, 2013
  EDA Café interviews Aldec Director of Sales, Keith McCann, at DVCon 2013
- FEB 27, 2013
  The latest in ASIC Prototyping News, Events and Resources
- FEB 26, 2013
  Aldec offers Advanced Screening of Functional Verification Platform’s Latest Release at DVCon 2013
- FEB 25, 2013
  Aldec Adds Assertions Training to Fast Track Online Program
- FEB 04, 2013
  Aldec Launches Free Online UVM Training
- JAN 29, 2013
  Follow Aldec. Win a Kindle Fire HD.
- JAN 07, 2013
  Hitachi Cable, Ltd. Deploys ALINT™ on Next Generation FPGA Design
- JAN 02, 2013
  Aldec Emulation and Verification Tools Adopted by Taiwan National Chiao Tung University for ESL Design Master’s Program
2012
- DEC 20, 2012
  Aldec Optimizes FPGA Routing Resources for Power and Performance
- DEC 17, 2012
  Now Available - Verification White Papers
- DEC 12, 2012
  EE TIMES: Mil-Aero Top 10 'How-To' articles for 2012, FPGA testing for DO-254 Compliance by Aldec
- DEC 12, 2012
  SEMIWIKI: Zynq out of the box, in FPGA-based Prototyping
- DEC 10, 2012
  Aldec Adds ARM Cortex-A9 Support to HES-7 ASIC Prototyping Platform
- DEC 04, 2012
  "Best of 2012" Top Webinars
- DEC 03, 2012
  Aldec unwraps SoC/ASIC verification platform at ‘Verification Futures 2012’ in Europe
- NOV 14, 2012
  Creonic Joins Aldec UNITE™ Partner Programme and Accelerates the Development of its IP Cores with Aldec Linting and Advanced Verification Tools
- NOV 05, 2012
  Aldec Boosts VHDL Simulation Performance
- NOV 05, 2012
  Aldec gives SoC Software Engineers early access to Hardware Aldec Inc. presents on Platform Validation at Verification Futures 2012
- OCT 29, 2012
  EE Journal Chalk Talk “Integrated Design Environment for FPGA” With Aldec Product Manager, Satyam Jani
- SEP 24, 2012
  Aldec Enhances Award-Winning Active-HDL with Flexible File Management to Manage Complex FPGA Projects
- SEP 17, 2012
  Aldec Enters ASIC Prototyping Market with HES-7™ Leveraging Xilinx’s Virtex®-7, HES-7 expands up to 96m ASIC Gate Capacity
- AUG 15, 2012
  SOC Central: Verific Design Automation's SystemVerilog, VHDL Parsers Linked with Aldec's Hardware Emulation Solution
- JUL 18, 2012
  Q3-2012 - Aldec™ Design and Verification Newsletter
- JUL 17, 2012
  TVS Validates UVM based VIP with Aldec’s Riviera-PRO Platform
- JUL 10, 2012
  Aldec and Agilent Technologies Bridge the Gap Between ESL and RTL by Linking Simulation Environments
- JUL 03, 2012
  Aldec invited to present "FPGA Level In-Target Testing for DO-254 Compliance" at Avionics Conference in South Korea
- JUN 13, 2012
  EDACafe: Aldec Update with Al the Robot and App. Engineering Director, Igor Tsapenko
- JUN 12, 2012
  DAC 2012 Wrap Up
- JUN 06, 2012
  EE Times: FPGA-based SoC Verification Challenges
- JUN 06, 2012
  Tech Design Forum: Where there’s a will… there’s a way to better VHDL verification
- MAY 31, 2012
  Open-Source VHDL Verification Methodology (OS-VVM) User Group to unveil Advanced Test Methodologies for VHDL Designers at DAC
- MAY 23, 2012
  Aldec at DAC 2012: 10 Face-to-Face Sessions
- MAY 22, 2012
  EE Times: FPGA Testing for DO-254 Compliance
- MAY 22, 2012
  Sigasi integrates Aldec Simulator to Accelerate Feedback Cycle
- MAY 21, 2012
  Tanner EDA and Aldec Deliver High-performance A/MS Solution for Mixed-signal IC Design and Verification
- MAY 09, 2012
  Verified: the need for continued VHDL support
- MAY 08, 2012
  EE Journal: Aldec Harnesses Massive Server Capacity
- MAY 01, 2012
  Aldec Israel to Serve Up the Latest in Functional Verification at ChipEx2012 in Tel Aviv
- APR 18, 2012
  Aldec Solutions Support Hardware Architecture of Zynq EPP at X-Fest 2012
- APR 12, 2012
  Q2-2012 - Aldec™ Design and Verification Newsletter
- APR 11, 2012
  EE Times: Automatic C-to-VHDL Testbench Generation Shortens FPGA Development Time
- MAR 20, 2012
  EDA Café: Testing Made Easy: Open Source VHDL Verification Methodology
- MAR 13, 2012
  Electronics Weekly: FPGA Verification for DO-254 is in the Hardware
- MAR 12, 2012
  Aldec Takes FPGA & ASIC Debugging to the Next Level
- MAR 12, 2012
  Electronics Weekly: Aldec Design Tool Supports UVM and new SystemVerilog
- FEB 29, 2012
  Aldec Launches DO-254 Practitioner’s Course with FAA DER, Randall Fulton
- FEB 20, 2012
  Aldec to Address Biggest Safety and Mission-Critical Verification Challenges in Electronic Warfare at EWCI in India
- JAN 23, 2012
  Aldec adds Documentation for Safety-Critical Designs in ALINT™ 2012.01
- JAN 19, 2012
  Q1-2012 - Aldec™ Design and Verification Newsletter
- JAN 13, 2012
  Verification Engineers are Invited to Take a Brief Survey and Receive a Chance to win an Ipad2!
- JAN 09, 2012
  Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM™
2011
- NOV 14, 2011
  Aldec Delivers Complete Support for UVM 1.1, Enabling VMM and OVM Interoperability
- OCT 31, 2011
  Aldec Releases Active-HDL 9.1 Supporting Simulation of the Newest FPGA Devices
- OCT 18, 2011
  Aldec presents ‘Automated Code Reviews for Fail-Safe Designs’ at ReSpace/MAPLD 2011 Conference in Albuquerque, NM.
- OCT 18, 2011
  Aldec presents 'FPGA Level In-Hardware Verification for DO-254 Compliance' at the 30th Annual DASC in Washington
- OCT 16, 2011
  IEEE: FPGA Level In-Hardware Verification for DO-254 Compliance
- OCT 06, 2011
  Aldec Confirms Platinum Sponsorship of 9th Annual International System-on-Chip (SoC) Conference
- OCT 06, 2011
  Q4-2011 - Aldec™ Design and Verification Newsletter
- SEP 14, 2011
  Aldec Honored for Superior FPGA Design and Verification tools
- SEP 13, 2011
  Aldec and Agnisys Partner to offer Closed Loop Verification Management to meet challenges in Verification of Modern Designs
- SEP 12, 2011
  Randall Fulton, FAA Consultant DER, to present DO-254 Training Seminar hosted by Aldec in Las Vegas, NV
- AUG 03, 2011
  Functional Verification Survey Winners
- JUL 25, 2011
  Aldec’s Emulation and Verification Tools Adopted by UC San Diego for the new Master’s Program in Wireless Embedded Systems
- JUL 21, 2011
  Q3-2011 - Aldec™ Design and Verification Newsletter
- JUL 11, 2011
  Aldec Adds UVM Transaction-Level Visual Debugging
- JUL 07, 2011
  Design your own Functional Verification Tool
- JAN 13, 2011
  Q1-2011 - Aldec™ Design and Verification Newsletter
2008
- SEP 22, 2008
  Aldec selected by Thales to deploy DO-254/ED-80 CTS for Level B Certification Compliance of Advanced Avionics System