Event Details View All Recorded Events Date Event Type Location Action May 08, 2025 FPGA Verification with VHDL and UVVM: New Features and Best Practices (US) Time: 11:00 AM - 12:00 PM (PST) Abstract Riviera-PRO includes a pre-compiled version of the latest UVVM, providing users with direct access to a robust verification methodology for VHDL designs. This latest version introduces significant new features, including Completion Detection and Detection of Unwanted Activity, further enhancing verification accuracy and reliability. UVVM simplifies the creation of VHDL testbenches and test sequencers, making them easy to write and understand — even for complex Devices Under Test (DUTs). Just as a well-structured (good) architecture is critical for FPGA design, it is equally essential for verifying complex designs. An effective verification architecture directly impacts efficiency and product quality. By adopting UVVM, teams can save hundreds of hours and reduce the number of design iterations significantly. Developed in close collaboration with the European Space Agency (ESA), UVVM extensions are specifically designed to meet these goals, ensuring robust and efficient verification. In this webinar, we will cover the fundamentals of UVVM, explore various features that enhance quality and productivity, and take a closer look at the latest enhancements introduced in this version. Agenda: Enabling Quality and Efficiency A simple TB architecture for a simple DUT UVVM: All the building block Important additional features for better quality and efficiency The new features Conclusion Q&A Webinar Duration: 45 min presentation/live demo 15 min Q&A Presenter BIO Espen Tallaksen is the CEO of EmLogic, in Norway.Espen is also the author and architect of the Open Source UVVM (Universal VHDL Verification Methodology), andhas a strong interest in methodology cultivation and pragmatic efficiency and quality improvementHe has given lots of technical presentations at various international conferences with great feedback. He is also giving courses on FPGA Design and Verification world-wide. Webinar Online Register
