Engineering Productivity Improved through Early Code Quality Checks

Date: Feb 5, 2018
Type: Release

Aldec’s Active-HDL tool now supports Unit Linting

 

Henderson, Nev. – February 5th, 2018 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has added a Unit Lint function to Active-HDL™ 10.5; where a ‘unit’ is a block of HDL code. The new feature works by running linting in the background enabling designers to quickly perform quality checks on just the code on which they are working - without leaving their design environment. This aids productivity in the long-run, because (full) chip-level linting can then be embarked upon with increased confidence.

 

“Performing a Unit Lint on a block of code during the coding phase of a project greatly minimizes the risk of encountering problems later in the project and helps reduce the number of design iterations that are purely correction-driven,” said Radek Nawrot, Active-HDL Product Manager. “Also, Unit Lint is a great way to enforce corporate coding standards early in the product lifecycle and to maintain consistency across the team.”

 

Unit Lint checks include: the identification (and an indication of the sensitivity) of incomplete and/or redundant combinational and sequential process logic; the identification of incomplete and/or redundant condition statements and unintended latches; confirmation of FSM coding correctness (including the detection of simple cases with dead and unreachable states); basic X propagation checks; the identification of data conversion coding errors (that can lead to sign and bit-width mistakes); and the flagging of suboptimal synthesizable code (such as deep priority logic and arithmetic resource sharing).

 

Active-HDL is a Windows-based, integrated FPGA design creation and simulation solution for team-based environments. The Unit Lint function runs Aldec’s ALINT-PRO in the background; provided the user has either the Expert edition of Active-HDL or a standalone license for the linter.

 

The full linting tool can also be launched from within Active-HDL, for chip-level linting where checks would typically include verifying clock and reset trees, checking for Clock and Reset Domain Crossings (CDC and RDC respectively) and evaluating the designs testability.

 

The Active-HDL 10.5 includes numerous new features, usability enhancements, and performance optimizations. For additional information, tutorials, free evaluation download and What’s New Presentation, visit https://www.aldec.com/en/products/fpga_simulation/active-hdl.

 

 

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, SoC and ASIC Emulation/Prototyping, Design Rule Checking, CDC/RDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solution, High-Performance Computing and Military/Aerospace solutions. www.aldec.com

Ask Us a Question
x
Ask Us a Question
x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.