What’s involved in simulation of a complex SoC FPGA like Versal ACAP?

As SoC FPGAs become more complex so do the verification challenges.

Henderson, NV, USA – February 8, 2024 - AMD’s Versal Adaptive Compute Acceleration Platform (ACAP) is a system-on-chip (SoC) device that builds on the capabilities and performance of the company’s highly successful Zynq 7000 and MPSoC families. The new device’s architecture includes three groups of engines:

• The Scalar Engines are used for functions and workloads that need scalar and sequential processing and include an ARM dual-core Application CPU (APU) and an ARM dual-core real-time CPU (RPU) with which users of MPSoC devices will be familiar.
• The Adaptable Engines are used for functions and workloads that need parallel processing and adaptable, dynamic configurable hardware for fast local memory access and custom I/Os. Again, MPSoC users will be familiar with these engines as they are essentially based on the programmable logic (PL) fabric that underpins traditional FPGAs.
• The Intelligent Engines are a combination of AI/ML and signal processing chipsets for functions and workloads that need vector processing, domain-specific parallel processing, and high compute efficiency.

The device also has many domain-specific IPs, such as PCIe gen 5, CCIX HBM and 600G cores. In addition, the Versal ACAP is the first AMD SoC FPGA to have a programmable network on chip (NoC). Its main role is to provide high-bandwidth memory-mapped access to all the hardware.

The different system blocks within Versal ACAP require different types of simulation and the use of variety of tools. Once each block has been simulated, and considered stable, it is safe to embark on system simulation.

A full system simulation environment can be created using Riviera-PRO and QEMU that simulates Versal ACAP’s programmable logic (PL), programmable software (PS) and AI engines; all without physical/target hardware. For further information, please see our article in emdedded.com.