Those Pesky SystemVerilog Interfaces...

SystemVerilog introduced numerous ideas new to Verilog programmers. Some of them enhanced hardware descriptions (e.g. always_ff block), some were meant to enhance verification (e.g. classes) and some were cross-over enhancements that can be used in many different contexts. SystemVerilog interface construct belongs to the cross-over group: it offers useful features for both hardware designers and verification engineers. The unfortunate side effect of this variety of applications is the confusion among SV users: all of them heard about interfaces, many used them to some extent, but virtually nobody fully mastered them.

To learn more, read our White Paper: Those Pesky SystemVerilog Interfaces