Aldec Design and Verification Blog Trending Articles Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Navigating VUnit: A Practical Guide to Modifying Testing Approaches In the two previous blogs, we introduced you to the world of VUnit, guided you through creating a project from scratch, and demonstrated how to run multi-threaded unit testing of multiple independent tests.... Tags:Aceleration,Functional Verification,HDL,Riviera-PRO,Simulation,Verification,VHDL Like(0) Comments (0) Read more Speeding Up Simulation with VUnit for Parallel Testing Effective simulation is essential in hardware development, as time and accuracy are critical factors that can determine the success or failure of a project.... Tags:Aceleration,Functional Verification,HDL,Riviera-PRO,SystemVerilog,VHDL Like(0) Comments (3) Read more Introduction to VUnit In the realms of HDL code verification, where precision and efficiency are crucial, a great hero has emerged; VUnit. This open-source framework for VHDL/SystemVerilog has been making waves in the industry,... Tags:Aceleration,Functional Verification,HDL,Riviera-PRO,VHDL Like(0) Comments (0) Read more Versal ACAP Simulation Challenges The electronics industry is all about optimization, and always has been. For example, you might think of system on chip (SoC) as a relatively recent term, coined this century. However, many regard the silicon that appeared in digital watches in the 1970s as constituting a system on a chip, ... Tags:Embedded,FPGA,Riviera-PRO,FPGA Simulation,Functional Verification,safety-critical,SystemC,SystemVerilog,VHDL,UVM Like(0) Comments (0) Read more Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it,... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(4) Comments (0) Read more ARM Cortex SoC Prototyping Platform for Industrial Applications Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms, such as Aldec HES-7™, provide a platform for designers to implement and verify functionality of... Tags:HES,Riviera-PRO,Functional Verification,FPGA,Aceleration,Emulation,ARM,Xilinx Like(1) Comments (0) Read more Using Plots for HDL Debugging A Powerful Alternative to Traditional Waveforms The most commonly used approach to analyzing objects in an HDL design is based on well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for... Tags:VHDL,Verilog,SystemVerilog,Riviera-PRO Like(1) Comments (0) Read more Fast Track™ to SystemVerilog for Verilog Users Aldec’s Latest Free Online Training Many experienced Verilog users tend to ignore SystemVerilog - mainly because high-end verification features of the new language are getting the majority of the attention in the press, and at conferences and trade shows. Those users may not realize that there are many SystemVerilog features that are very useful for... Tags:Riviera-PRO,Functional Verification,SystemVerilog,Verification Like(1) Comments (0) Read more Those Pesky SystemVerilog Interfaces... SystemVerilog introduced numerous ideas new to Verilog programmers. Some of them enhanced hardware descriptions (e.g. always_ff block), some were meant to enhance verification (e.g. classes) and some were cross-over enhancements that can be used in many different contexts. SystemVerilog interface... Tags:Functional Verification,Riviera-PRO,SystemVerilog Like(1) Comments (0) Read more Fastest Co-Simulation Interfaces For MATLAB®, Simulink®, SystemVue® Aldec Riviera-PRO™ offers the fastest direct co-simulation interfaces with MathWorks MATLAB® & Simulink® and Agilent SystemVue®, enabling multi-domain electronic system-level (ESL) design flow for DSP, RF, and FPGA/ASIC design.... Tags:Riviera-PRO,Co-simulation,ASIC,FPGA Like(1) Comments (0) Read more
