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Fastest Co-Simulation Interfaces

For MATLAB®, Simulink®, SystemVue®

Mariusz Grabowski, FPGA Design and Verification Engineer
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Aldec Riviera-PRO™ offers the fastest direct co-simulation interfaces with MathWorks MATLAB® & Simulink® and Agilent SystemVue®, enabling multi-domain electronic system-level (ESL) design flow for DSP, RF, and FPGA/ASIC design.

Related Application Notes:

MATLAB – HDL Interface in Riviera-PRO and Active-HDL

Controlling Riviera-PRO from MATLAB

Using Agilent SystemVue® Co-Simulation Interface

FPGA Prototyping Using Agilent SystemVue and Aldec Riviera-PRO

Tags:Riviera-PRO,Co-simulation,ASIC,FPGA

Mariusz Grabowski is an FPGA Design and Verification Engineer at Aldec. He works in the field of verification for DO-254 compliance as well as developing digital processing systems. He is proficient in digital design and verification, using hardware description languages such as Verilog/SystemVerilog and VHDL, and the use of verification methodologies such as UVM.

Mariusz is a student at the AGH University of Science and Technology in Krakow, Poland. He also gains practical experience in the AVADER Scientific Group (where he designs novel vision systems on FPGAs) and in the Integra Scientific Group (where he acquires knowledge about microprocessor systems and electronics).

  • Related resources
  • Products:
  • Riviera-PRO
  • Advanced Verification

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