Scaling the “Internet of Things”

Happy New Year!

January brought an unseasonably warm wave of weather to Las Vegas as International CES converged on the city this month.

The size and scope of this worldwide consumer electronics tradeshow continues to grow each year with new products and industries on the rise, now driven by a phenomenon called the “Internet of Things” (IoT).

Shawn Dubravac, Ph.D., Chief Economist and Director of Research for the Consumer Electronics Association (CEA) kicked off the event by presenting a summary of his new book, “Digital Destiny”.

According to Dr. Dubravac, the electronics industry is at another inflection point as digital technology continues to replace legacy analog technologies. There are 1.7 billion personal computers in the world today, now eclipsed by 2 billion smart phones.  But the “Internet of Things” (IoT) could produce 50 billion smart, connected sensor modules that communicate with each other and can be aggregated as “Big Data” to work on important social issues.  These electronic modules could potentially be embedded in every device that we own, from smart home appliances, to the cars we drive, and even inside the clothes we wear.

This is good news for digital design and verification engineers as digital logic circuitry will continue to be an important component within each of those 50 billion devices over the next decade.

For the last thirty years, Aldec has been promoting the benefits of employing digital design and verification solutions that interface computer-aided design software tools with embedded-circuit hardware platforms.

“Virtual Hardware” (VH) is a design entry tool that has an on-line, real-time interactive background simulator. Each device drawn on the VH screen behaves functionally like the actual part, down to the last detail.

Since the VH parts can interact with real hardware, the technology allows new forms of design entry and verification. The multiple uses of Virtual Hardware are only now being explored. They should lead to further simplifications of the design process.”

--“An Introduction to Digital Design Verification” by Stanley Hyduke, March 1996

Scalability of design size, quantity of emulators, simulation speed, rapid digital logic prototyping, and the integration of reusable IP, are just some of the benefits that come from the marriage of a digital software simulator with a large-scale FPGA hardware platform.  Today, millions of ASIC gates can be modeled on just a single Xilinx Virtex-7  Field Programmable Gate Array device. The Aldec HES-7™ FPGA high speed prototyping boards can model up to 24 million ASIC gates with just two Xilinx Virtex-7 FPGAs and up to 72 million ASIC gates with six Xilinx Virtex-7 FPGA, enabling different modes of verification including traditional prototyping, simulation acceleration and transaction level emulation.

Multiple HES-7 FPGA development boards can be “bussed” together to accommodate even larger designs that comprise 100s of millions of ASIC gates.

Instead of limiting the company product line to a fixed, dedicated hardware emulation platform, Aldec has developed a hardware design and verification system with an open architecture that can quickly migrate to each next-generation FPGA technology.

This allows FPGA and ASIC design engineers to easily develop their own custom in-house prototyping boards and systems that encourage scalability and IP reuse in the following areas:

• IP is transferable across the latest FPGAs developed by multiple manufacturers    
• Scalable hardware platforms can be developed with backplane or extension slots
• Design size can be scaled incrementally while also enabling parallel synthesis and implementation
• Design simulation speed can be accelerated incrementally and emulation clusters can be embedded in the design.
• Developed IP can be reused by different teams for simulation, emulation and prototyping.

During International CES, the Zigbee Alliance demonstrated what a smart, connected home can look like today if each LED light and individual appliance were its own node on a local, wireless mesh network. Each individual device in an entire home could be controlled locally and remotely through a 2-inch cube that, when plugged into a wall socket, became always on and always connected to a homeowner’s mobile phone or smart watch.

To model all the interaction and scalability of these digital devices in a smart home requires a versatile design platform that can show the behavior of each individual device and its interaction with all other devices.

The ability of HES-DVM™ to create emulation clusters that can individually model the behavior of each node in a wireless network allows the smart home appliance designer the flexibility to begin scaling “swarms” of interconnected, digital IP onto the Internet of Things.

At the same time, an open design and verification architecture can integrate more processing capabilities to scale with each new requirement demanded by the evolving electronic design automation industry.

Software simulation has become more flexible and adaptable to hardware and firmware, enabling acceleration of design and verification. With HES-DVM, customers can interface third-party simulators, as well as simulate and verify directly with Aldec Active-HDL and Riviera-PRO product lines.

Increasing use of automated processes in Aldec’s tool sets can simplify and accelerate design setup by providing:

--A complete toolset for design setup – DVM.

--A design compilation front-end that supports the latest standards of SystemVerilog and VHDL.

--Behavioral compiler for transactors supporting SV DPI-C and implicit state machines (ISM).

--Incremental design synthesis with third-party synthesis tools.

--Self-constrained and automated implementation with FPGA vendor tools such as Xilinx Vivado.

--Automatic and guided partitioning.

--Automatic gated clock conversion with unlimited number of clock domains.

--Memory flow to map design memories to a printed circuit board or to FPGA resources.

--Debugging-aware design processing with automatic code instrumentation.

--Parallel computing with LSF and SGE, as well as design setup scalability.

--TCL Scripting and GUI available

Debugging capabilities have also incrementally improved over the years as the size and scope of design projects continue to grow. Advanced features include:

--HVD technology for 100% visibility with reduced number of captive probes.

--Configurable triggering

--Hardware breakpoints

--Clocks control (Stop, Run, Step)

--Debug data stored in waveform files: ASDB for Riviera-PRO and FSDB for Verdi.

--Memory backdoor access for read and write operations

--HW Debugger tool with GUI to manage debug process locally, as well as remotely via LAN.

--C/C++ HES Debug API

For 30 years, Aldec engineering teams have contributed to the growth of the Electronic Design Automation industry.

This month, Aldec released version 2014.12 of HES-DVM.  Come take a look at its newest features, including:

--Configurable Board Definitions

--Design Finder that speeds up hierarchy search and filtering

--Improved LSF Farm Support

--SCE-MI 2 Transactors Behavioral Compiler

--SCE-MI 2 Clocks Turbo Mode

--Support for DPI-C exported tasks

--Support for plusargs

--Force Signal Value

--Constant Arguments Optimization

We invite you to join us as we continue to scale the new “Internet of Every Thing”. 

Wishing you all the best for a happy and productive 2015!

For more on HES-DVM, visit www.aldec.com/products/hes-dvm or email sales@aldec.com.