Event Details View All Recorded Events Date Event Type Location Action Mar 13, 2025 Maximizing Design Reliability with Advanced Linting: Uncover Hidden RTL Issues Early (EU) Time: 4:00 PM - 5:00 PM (CEST) Abstract Undetected RTL coding issues can lead to costly design iterations and unexpected failures late in the development cycle. Advanced linting is a powerful static analysis technique that detects bugs, inefficiencies, and structural issues in RTL code—long before they manifest in hardware. Linting tools analyze HDL code against hundreds of industry-proven design rules, covering syntax, naming conventions, synthesizability, and performance optimizations. They also help detect clock domain crossing (CDC) issues, reset tree problems, and RTL-to-synthesis mismatches—errors that often remain invisible in functional simulations but can cause failures in FPGA lab testing. In this webinar, we’ll explore the key benefits and best practices of advanced linting for robust and efficient design development. Through practical examples, we’ll demonstrate how linting can improve code quality, enhance design reuse, and prevent late-stage surprises. Agenda: Overview of the Advanced Linting Process Best Practices for Effective Linting in RTL Design Real-World Linting Examples: Identifying functional bugs early Optimizing code for synthesis and implementation Enhancing design quality and reusability Detecting clock/reset tree and CDC issues Key Takeaways & Q&A Presenter BIO Alex Gnusin, Aldec’s ALINT-PRO Product ManagerAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology. Webinar Online Register
