Functional Verification Survey Winners

Date: Aug 3, 2011
Type: Company

Henderson, NV — August 1, 2011 Aldec extends a sincere thank you to the hundreds of engineers from around the globe answered the call for Aldec’s Functional Verification Survey in recent weeks. Many of the innovations in verification that Aldec has delivered in the past 27 years, including Mirror-Box Technology, and countless others have been in direct response to feedback from the Design Verification community.

To show our appreciation for those who provided feedback in our survey, Aldec has conducted a raffle for some great prizes. As promised, here is the announcement of winners:

Grand Prize Winner
(Apple® iPad 2):
  • Benjamin G.
Runner-up Prize Winners
(Apple® iPod shuffles):
  • Aula Franks and (name withheld)

Aldec also remains committed to providing world-class Verification educational opportunities, created with feedback and input from the design engineering community.

Upcoming free Verification training events include:

Live Webinar: SystemVerilog: Who? What? When? Where?

Thursday, August, 25, 2011

This presentation explains which areas of SystemVerilog should be implemented by hardware designers. Main topics include Design Subset, Assertions, Verification Subset, Verification Methodologies (OVM/UVM).

Lunch and Learn Seminar: Assertions for HDL designers

Thursday, August 18, 2011

Santa, Clara, CA

This half-day seminar is for hardware designers with practical knowledge of Verilog and/or VHDL. It prepares the student for practical usage of assertions in verification tools by explaining basic ideas, introducing key elements of assertions illustrated with simple examples and presenting complete design demonstrating various uses of assertions. Examples use SystemVerilog Assertions (SVA) and Property Specification Language (PSL) in parallel, giving students more options of further study. For a printable event flyer, please click here.

To learn more or to register for these events, we invite you to visit

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

Media Contact:

Christina Toole
Marketing Manager
Aldec, Inc.
+(702) 990-4400
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