Aldec and Agnisys Partner to offer Closed Loop Verification Management to meet challenges in Verification of Modern Designs

Date: Sep 13, 2011
Type: Company

Henderson, NV – September 13, 2011 – Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced that it has forged a partnership with Agnisys, Inc. to collectively offer closed loop verification of digital designs.

Every complex verification environment has numerous data sources which need to be managed – design and verification source code, regression data, bug tracking data, requirements, verification plans and more. Collating and mining these data sources provides an opportunity for verification teams to reduce their costs and get to faster verification closure.

“This partnership will enable Riviera-PRO™ customers to speed up the verification process, have a clear verification analysis capability and spend less time doing verification management and debug. The IVerifySpec™ tool from Agnisys combines information from all available sources pertaining to verification and gives the user the ability to monitor and control verification from a single location.” said Igor Tsapenko, Director of Research and Development.

“Large Verification projects need tools such as Rivera-PRO™. It’s openness and ease of use made it possible for us to easily link it with IVerifySpec™. The capabilities of Aldec’s simulation engine and IVerifySpec™ are complementary, so this is a very valuable strategic partnership for us.” said Anupam Bakshi, CEO at Agnisys, Inc.

Recorded Webinar: Closed Loop Verification of Large Designs

Demonstrates how verification planning, simulation and regression management can be easily handled using Agnisys and Aldec tools. Click here to download.

About Aldec
Aldec, Inc., is an industry-leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. To learn more visit and follow Aldec on Twitter @

About Agnisys
Agnisys helps cost-conscious IP/FPGA/SoC companies to improve quality and productivity. IDesignSpec™ is a tool that enables teams to capture hardware registers in Word, Excel, OpenOffice and generate any code (UVM, OVM, VMM, RTL, C-headers etc.) from it. IVerifySpec™ is a web-portal for verification planning and management. It enables teams to create agile, collaborative verification plans and monitor their execution. IAssertSpec™ is a tool for assertion based design and verification. It helps teams to create assertions that match the product specification. Additional information is available at and on twitter at @agnisys.

Riviera-PRO is a trademark of Aldec, Inc. IDesignSpec, IVerifiSpec and IAssertSpec are trademarks of Agnisys, Inc. All other trademarks or registered trademarks are property of their respective owners.

Media Contact: Christina Toole,
Marketing Manager
Aldec, Inc.
+(702) 990-4400
Agnisys, Inc.
Guy Haas
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