Q1-2012 - Aldec™ Design and Verification NewsletterDate: Jan 19, 2012 Type: Newsletter Looking Back – and Ahead to the Next 30 Years Two years from now, Aldec will celebrate a milestone - 30 years of innovative service to the Electronic Design Automation industry. Working with designers in the field since the birth of EDA, Aldec has had a front row seat to witness the recent decades’ astonishing surge in technology. From smart phones to advances in medical safety and aviation, few outside the industry realize without the diligent electronics designer aided in the lab by innovative EDA tools - the life changing advances we take for granted today would not exist. Fewer EDA tool providers competing for their business (thanks to a steady stream of recent mergers and acquisitions) has left some customers asking if the future of EDA will hold less innovation, support and service – at a higher price. At Aldec, our customer-centric business model ensures that we will continue to revolutionize the industry with exciting tools delivered to serve real-world needs of our customers. Riviera-PRO Delivers Complete Support for UVM, Enabling VMM and OVM Interoperability Riviera-PRO™ offers complete support for the Universal Verification Methodology (UVM) Version 1.1, and enhances the SystemVerilog verification methodology by providing extended language construct support and adding debugging and productivity features in the waveform. The new language construct enhancements, based on an industry accepted IEEE 1800™-2009 standard, enable customers to do extensive debugging and provide a path to support for UVM together with previous Open Verification Methodology (OVM) and alternative Verification Methodology Manual (VMM) methodologies. Read More With the release of Riviera-PRO 2011.10, Aldec supports the latest version of UVM and related extensions OVM/VMM Interoperability Kit, enabling OVM- and VMM-based IP to work together in a single verification environment. The kit contains OVM/VMM interoperability library – a collection of adapters and utilities that enables efficient reuse without the need to modify the legacy code. UVM Register Kit, enabling easy migration path from OVM to UVM-based verification environment. The kit contains a part of the Accellera UVM reference library – a standard vendor independent register solution that enables migration to UVM without changing the use model. UVM 1.1 is immediately available with Riviera-PRO 2011.10 installation today. For additional information about Riviera-PRO, including tutorials, downloads, and a "What's New" presentation, please visit www.aldec.com/en/products/functional_verification/riviera-pro. Active-HDL 9.1 Supporting Simulation of the Newest FPGA Devices The latest release of Active-HDL™, an award-winning HDL-based FPGA Design and Simulation solution, supports design creation and simulation of the newest industry-leading FPGA devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Tabula, Quicklogic® and Xilinx®. Known to FPGA designers as a tool-of-choice for ease and convenience (with design creation, documentation, code coverage and simulation bundled into one product) the latest release of Active-HDL includes even more benefits such as: Read More Integration with Aldec Riviera-PRO™ verification products - providing a gateway to 64-bit simulation and SystemVerilog Verification HDL Code Browser Tool for on-the-fly error detection prior to compilation Unified Coverage Database – a new single source database to manage different types of coverage Enhanced support of VHDL-2008 and PSL/SVA Assertions For additional information about Active-HDL 9.1 including tutorials, downloads and a What’s New presentation, please visit www.aldec.com/en/products/fpga_simulation/active-hdl. OS-VVM™ named Product of the Week by Electronics World for Delivering Randomization Capabilities to VHDL Designers Open Source - VHDL Verification Methodology (OS-VVM™), recently named Electronics World Product of the Week, delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, providing advanced features to VHDL design engineers while enabling them to continue to develop using VHDL. Read More Benefits of OS-VVM It provides access to advanced randomization and functional coverage capabilities (previously available only within system-level methodologies) that can be used in any testbench; Rather than using a constraint solver, balance in the randomization is achieved by interacting with the functional coverage model, resulting in fewer cycles; The initial randomization is refined by using procedural code which can easily mix directed, algorithmic, file-based methods and additional randomization; and A straightforward usage model, ensuring users are able to get up to speed quickly while retaining the freedom and flexibility to continue using VHDL. Availability Aldec tools offer the advanced randomization and functional coverage capabilities provided by OS-VVM with a simple flip of the VHDL-2008 switch; i.e.no additional licenses are required. SynthWorks, the maintainer of the OS-VVM, offers in-depth training for OS-VVM and supplements with additional packages for creating scoreboards, memories, and abstracting interfaces. To download the free OS-VVM packages and view additional resources, including a white paper, user guide, sample designs, and VHDL package source files please click here. Hardware Visibility-based Debugging (HVD™) Technology, Provides 100% Visibility During Hardware Emulation Built into the emulation solution, Aldec’s HVD (Hardware Visibility-based Debugging) technology analyzes RTL code to identify the minimal set of debugging probes that must be present in the emulation hardware to guarantee 100% visibility. During the emulation runtime, the HVD based data extender calculates any design probes that have not been captured directly from the emulator. For a typical SoC design, this reduces the amount of data required to be preserved and captured from the emulator to 30% (70% saving). Additionally, both dynamic and static probes from emulation can be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and complete traceability to the designs RTL source code. Read More Until now, hardware designers were forced to use multiple applications in addition to their simulator and emulator to ensure proper hardware signal data extraction and visualization. With HVD technology, Aldec facilitates a fully integrated debugging solution with improved functionality and simplified debugging flow. Designers will be able to use the familiar debugging features of Riviera-PRO during emulation and eliminate the unnecessary steps of database conversion. To view HVD Technology resources, including an interactive movie, please visit www.aldec.com/en/solutions/hardware_emulation_solutions. Advanced Standalone Reporting to Facilitate Design Reviews With the latest release of ALINT, product version 2012.01, even completely new users can create and distribute interactive reports in a few minutes without the knowledge of any details about the design that is being checked, tool’s configuration, commands, and command line switches. Typically it takes less than one hour to set up and check a relatively complex design and deploy the appropriate interactive report on the corporate intranet or version control system. Read More The new Standalone Reporting feature enables completely independent reports that can be viewed with any standard web browser at any computer, with no additional ALINT license required. These new Standalone reports include just everything you would expect from a dedicated feature-rich GUI application, including the tools for navigation through the design hierarchy, coding standard violations analysis, and cross-probing from the violation reports to the source files for quick investigation, thus providing a complete insight into the quality of design at the current point of development cycle. For more, please visit www.aldec.com/en/products/functional_verification/alint-pro. Standardized Coverage Driven Verification Do you think that vendor specific coverage database format is not sufficient when it comes to overall coverage driven verification? Coverage metrics can come from different sources such as simulation, formal verification, equivalence checking, static design checking etc. There are different vendors that provide tools/solution for each of these categories. But each vendor has their own proprietary coverage database format which keeps users from mixing verification management tool and simulator from different vendors in their flow. Read More Accellera has been working on Unified Coverage Interoperability Standard (UCIS) which will facilitate the portability across multiple vendors and enable the innovation for the next generation of coverage tools. Additional benefits of UCIS compliance coverage database: It can store coverage data from the entire simulation or a snapshot made at any moment of the simulation process Merges coverage data from multiple simulation runs into a cumulative database (temporal, spatial, and heterogeneous use cases) API that allows transferring coverage data between different vendors Aldec.com delivers New Features and Enhanced User Functionality Aldec.com has a new look, fresh content, new features and enhanced functionality. With a new site fully integrated with Aldec's contact database, visitors will no longer have to register for every download. Instead (once logged in) users will have access to Aldec’s Support Portal, as well as Downloads, Registrations and other Resources. We invite you to click here to take a tour today, and take advantage of the 'Feedback' button to share your thoughts on the new site. We appreciate your feedback as we continually seek to improve our customer support experience. DO-254 Training Seminar Results: Exceeding the Expectations The recent DO-254 training seminar held Las Vegas, NV was well received by attendees. Notable firms in attendance included BAE Systems, Eaton, L3 Communications, Moog and Thales Avionics as well as other leading avionics companies representing four different countries. Attendees learned how to create and organize requirements by functional elements such that they are traceable and verifiable, as well as how to develop normal and robust test cases such that they are re-usable in simulation and in-circuit tests. Read More More importantly, they discovered the significance of in-hardware verification methodology for DO-254 compliance provided by Aldec's DO-254/CTS. Comments indicated that the training was engaging, insightful, informative and unique - surpassing the expectations of the attendees. "I enjoyed this class", "One of the best seminars I've attended", "Found the examples very informative", "Was most interested in the test case approach as it was simplified compared to what I am used to". Aldec will be holding more DO-254 trainings in North America in the future, please contact our team at training@aldec.com and let us know which topics interest you most. To learn more about DO-254 training courses offered by Aldec with FAA DER, Randall Fulton, please visit www.aldec.com/en/products/mil_aero_verification/do-254. Product Updates ALINT™ 2012.01 The new release of ALINT brings valuable tools for efficient project collaboration and information sharing across your organization. These new tools include: Interactive HTML Reportingthat enables efficient design analysis even without the tool installed. This new report delivers a unique experience of interactive violation report analysis in a comfort of your favorite web browser. Enabling almost all the features of the dedicated Violation Viewer, including the cross-probing, it is absolutely portable and independent from the design and its sources. Exclusion Files Annotation, the essential tool for project documentation that enables justifying every waiver introduced. Every single exclusion can be justified now and the appropriate comments appear in the Violation Viewer (applies when “irrelevant” coding standard violations are not filtered out). Windows 64-bit linting. With a dedicated build for 64-bit Windows® platform available, the tool is free of memory limitations previously imposed by the 32-bit computing environment and is capable of analyzing truly large and memory hungry designs. In addition, we have implemented numerous productivity features based on requests coming from our customers – make sure to leverage all these benefits as soon as the new build is available! Riviera-PRO™ 2012.02 (Available February 2012) The last release of Riviera-PRO, version 2011.10, delivered a pack of new productivity features, support for the new language constructs in VHDL’2008 and SystemVerilog’2009, and incremental updates of the verification libraries shipped with the tool. In 2012, Aldec continues developing Riviera-PRO at the traditional fast pace, delivering 3 major releases per year. The next version, Riviera-PRO 2012.02, scheduled to arrive in February’2012, is coming with an array of new debugging features. For example: Message Bar in the Waveform Viewer gives the insight into messages that were output from the simulator during the runtime. Support for viewing SystemVerilog class objects is another example of new debugging functionality which provides a more natural way to comprehend and debug sophisticated verification environment. Looking further at the Waveform, significant improvements have been introduced to virtual groups, enabling creation of complex hierarchical structures with an arbitrary number of levels. Assertions is yet another area addressed by Riviera-PRO 2012.02, so that you can observe the SystemVerilog assertions based on multiclocked sequences and properties in the GUI. Riviera-PRO 2012.02 brings not only the debugging features, but new language standard constructs as well. As always, Aldec highly encourages you to download and use the latest versions of software to leverage all the benefits available. Active-HDL™ 9.1 Active-HDL 9.1 includes many new features and numerous enhancements to simplify team-based designing and to increase productivity. Along with our main focus of providing robust support for latest language standard such as VHDL-2008 and SystemVerilog 2009(Design constructs). Additional features include: New Code Browser tool for better navigation inside HDL code and on-the-fly error detection before compilation Direct interface to Aldec solutions to allow users to move between products more easily Support for latest FPGA devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Tabula, Quicklogic® and Xilinx® Unified Coverage Interoperability Standard (UCIS) compatible coverage database – Preview Numerous enhancements in HDL Editor – Phrase highlighting, Auto-complete signal name, Zooming functionality Active-HDL™ Student Edition (Available February 2012) The upcoming release of Active-HDL Student Edition is packed with many new features and enhancements to provide students a robust tool with support for latest language standard and FPGA devices. Major highlights for this release include: Support for VHDL 2008 and SystemVerilog 2009 (Design Constructs) Support for latest FPGA devices in Design Flow Manager Code2Graphics tool to convert HDL source code into block and state diagrams Documentation tool to export projects to HTML and PDF Products Riviera-PRO™ 2011.10 Advanced Verification Platform (OVM/UVM, VMM) High-Performance Simulator Assertion-Based Verification Code and Functional Coverage Transaction-Level Debugging DSP Co-Simulation with MATLAB® Active-HDL™ 9.1 FPGA Design & Verification Mixed-Language Simulator Assertions Coverage Tools PCB Interface Documentation Tools ALINT™ 2012.01 Early Bugs Detection Phase-Based Linting Methodology Over 400 Design Rules VHDL, Verilog®, & Mixed User-defined Rules Integrated Debugging Environment HES-DVM™ 2011.10 7MHz Emulation Speed, 37 Million ASIC Gates SCE-MI 2.0 DPI-C Support Integration with Riviera-PRO: Adding/Removing Debugging Signals and Emulation Start/Stop/Step Dynamic Triggers - Flexible Probes About AldecHeadquartered in Henderson, Nevada, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. Did You Know?The Signal Alias Editor in Active-HDL™ allows you to assign your own easy-to-recognize design mnemonics to real values of signals displayed in the Memory or Waveform Viewer windows. Waveform Viewer is now also able to represent vectors as a fixed-point numbers.Preference Manager inside Active-HDL™ allows you to export and import the tool preferences. Now, tool settings can be retained when you move between the versions. Tool preferences from previous version can be exported to a file which later using preference manager can be imported back to the new version. Preference Manager can be invoked by executing the prefman.exe file located in the \Bin sub-directory of Active-HDL installation folder.Code Templates integrated with Riviera-PRO HDL Editor enable you to define custom code templates with auto-complete mnemonics and variable fields (the variable-based templates enable quick change of special fields that occur multiple times within a code template – while editing a first occurrence of a variable field, the other occurrences of this field are updated automatically). Once the templates are saved to an .xml file, they can be shared across your company to facilitate code editing and standardization.You can use the built-in classifications (such as "differences between the RTL and post-synthesis simulation" or "synchronous reset guidelines") to address the violations related to a particular part of your coding standard. To do that, you just need to drag-and-drop the appropriate subset/branch from Rule Plug-in Viewer to the Violation Viewer. This adds a quick auto-filter and enables you to focus on the topic of your concern.
