Tech Design Forum: Where there’s a will… there’s a way to better VHDL verificationDate: Jun 6, 2012 Type: In the NewsWhere there’s a will… there’s a way to better VHDL verification Tech Design ForumEE Times: FPGA-based SoC Verification ChallengesDate: Jun 6, 2012 Type: In the NewsFPGA-based SoC Verification Challenges EE Times
