Aldec Boosts VHDL Simulation PerformanceDate: Nov 5, 2012 Type: ReleaseHenderson, NV - November 5, 2012 – Aldec, Inc. announced the release of its mixed language advanced verification platform, Riviera-PRO™ 2012.10. The release delivers numerous stability and performance improvements, support for the latest versions of industry-standard SystemVerilog verification libraries, new language constructs, new debugging tools, and improved interfaces to other industry leading EDA tools. Riviera-PRO delivers a 20% VHDL simulation performance gain over previous releases. “We keep developing and delivering not only new productivity features, but also innovative core engine optimizations to boost simulation performance in VHDL and SystemVerilog to support the complexity and capacity of today’s designs,” said Mariusz Dykierek, Aldec R&D Project Manager. “Easy-to-use debugging tools and a powerful mixed language simulation engine are in high demand. Aldec continues to help our customers reduce design cost and time and bring their products to market quickly.” Highlights of Riviera-PRO 2012.10: Core Simulation Engine Simulation performance improvements – VHDL simulation now up to 20% faster! New language constructs in SystemVerilog’2009 and VHDL’2008 Support for the latest verification libraries – UVM 1.1c, SystemC 2.3.0, OS-VVM™ Increase Stability on large multi-million gate designs Framework and Productivity Waveform enhanced for displaying of composite objects (virtual arrays) Possibility to rename objects in the waveform, and context search Additional operations using the drag-n-drop method 3rd Party Interfaces The new way to use MATLAB co-simulation interface – Invoke Riviera-PRO from MATLAB The latest precompiled simulation libraries for Altera and Xilinx FPGAs Compatibility with the latest release of Xilinx Vivado™ Design Suite supporting Virtex-7 FSDB updated to the version 5.0 – Compatible with Verdi3 2012.07 Complete list of new features and enhancements: Riviera-PRO 2012.10 Release Notes “What’s New” presentation: Riviera-PRO 2012.10 What's New Availability Riviera-PRO 2012.10 is available today. Download the latest release from www.aldec.com/downloads. Current customers with valid maintenance receive the release at no additional cost. About Aldec Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners. Media Contact: Christina Toole, Aldec, Inc. +1.702.990.4400christinat@aldec.comwww.aldec.com Aldec gives SoC Software Engineers early access to Hardware Aldec Inc. presents on Platform Validation at Verification Futures 2012Date: Nov 5, 2012 Type: ReleaseHenderson, NV – November 5, 2012 – Aldec, Inc. is presenting a paper on Platform Validation at Verification Futures 2012 in Windsor, United Kingdom, on Monday 19th November; where Platform Validation is at the heart of SoC hardware and software co-verification, and currently one of the EDA industry’s hottest topics. With technology trends, such as embedded processors, and time-to-market pressures, concurrent engineering demands that software engineers have early access to silicon. Platform Validation extends beyond the realms of hardware design simulation and functional verification (for which Aldec is perhaps best known) and pushes into system hardware and software co-verification. Jacek Majkowski, Senior Hardware Engineer with Aldec will be presenting the Platform Validation paper and comments: “Whilst embedded system complexity is growing very fast, driven by high customer expectations, verification tools need to keep pace by providing hardware-based methodologies for SoC designers. The complexity grows in both setup of the design under test and the runtime stage of the test. With Aldec’s new HES-7™ platform, setup of the high capacity designs is far simpler with the ability to scale the available capacity of the tool, while Standard Co-Emulation Modeling Interface (SCE-MI) interface provides an efficient and standardized way to test the design on an emulation platform.” Importantly, Aldec provides simulator and hardware boards with software that automates (design) mapping to FPGAs. In addition, thanks to Universal Verification Methodology (UVM), SCE-MI methodologies and supporting hardware/interfaces, it is possible to move freely between hardware simulation, emulation and system prototyping. Moreover, Aldec’s HES-7 boards can be used in different configurations at different phases of a project. For example, four boards (with two Xilinx® Virtex®-7 FPGAs each) could be used by four engineers (hardware or software) as desktop prototyping platforms; to work on separate parts of the design. Moving toward system integration, a backplane can be used to connect the four HES-7 boards together; delivering the equivalent of 96 million ASIC gates. Majkowski’s presentation will cover an overview on transaction-based verification technologies, including SCE-MI macro-based and Direct Programming Interface (DPI) function-based synthesizable transactors, eliminating communication bottlenecks that could compromise the performance of hardware emulation systems. Real-life use cases will be shown, as well as two detailed customer case studies on transaction-based verification of large ASICs. Now in its second year, Verification Futures is organized and run by test and verification services company TVS and the Electronic Chips & Systems design Initiative (ECSI). Engineers wishing to register to attend Verification Futures 2012 in Windsor on 19th November can do so by clicking here. About Aldec Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners. Media Contact: Christina Toole, Aldec, Inc. +1.702.990.4400christinat@aldec.comwww.aldec.com
