Aldec to offer ‘DAC CHAT’ Technical Sessions Live Online

OSVVM provides functional coverage and randomization utilities that layer on top of transaction level modeling based VHDL testbench to create either basic Constrained Random tests or more advanced Intelligent Coverage based Random tests.  This simplified approach allows utilization of advanced randomization techniques, which can also be easily mixed with directed, algorithmic, and file-based test generation techniques.

Requirements are the basis of the verification activities for safety-critical FPGAs. Safety-critical industry standards for avionics, industrial and automotive enforce a requirements-based verification process to ensure safe and reliable FPGAs. Learn in this webinar the associated challenges to requirements management and verification management for safety-critical FPGAs and uncover a solution for requirements management, traceability, impact analysis, test plan management and verification management.

As today's SoC and ASIC designs evolve to integrate the latest embedded processors, media interfaces, and high-speed serial communication, FPGA prototyping platforms are struggling to maintain the pace of designs surpassing the 100 million ASIC gate count. With the evolution of modular architectures and robust scalable backplanes, FPGA prototyping vendor solutions such as Aldec HES-7™ are able to keep pace with hardware designers.

Early access to the emulation platform allows HW/SW teams to work concurrently, enabling HW/SW co-design and co-verification. This webinar outlines a solution that allows using FPGA boards in different modes; simulation acceleration, transaction-level emulation or integrated with virtual platforms. Another option is in-circuit emulation with speed adapters that provide a high-speed hardware interface. 

Standard Co-Emulation Modeling Interface (SCE-MI) is Accellera's standard for bridging two realms: untimed (HVL, testbench on host) and timed (HDL, design in emulator). SCE-MI offers the flexibility to choose an emulation platform and become vendor independent, critical today when advanced FPGA technology allows for building fast and large capacity emulators at a fraction of the cost.

Design Rule Checks have traditionally been associated with large ASIC designs and have been used effectively to catch static violations as early as possible, hereby reducing debug time in the subsequent verification process. The benefits are the same when using DRC in the design methodology of FPGA. This webinar outlines a solution that offers advanced check for structural CDC issues, extensive coverage of industry standard design rules, and addresses issues early in the design cycle.