Aldec @ DAC 2015: Scalable Prototyping, UVM Simulation, Productivity Gains using Python and More

Henderson, NV – May 26, 2015 – Aldec, Inc. a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, once again delivers free technical sessions at the Design Automation Conference (DAC), June 7-11, 2015 in San Francisco, California.  

 

Technical Sessions and Demos

Daily (June 8-10, 2015) at Booth #1725

Spots fill up quickly. Register to reserve your free, in-depth technical session.

Session 01: Scalable Prototyping in FPGA up to 633 Million ASIC Gates
Session 02: Using Chip Control View for Efficient Structural CDC Analysis
Session 03: The Pythonic Tonic: Miracle cure or Snake-oil?
Session 04: SoC Pre-silicon bring-up in Co-emulation with ARM® FAST MODELS Virtual Platform
Session 05: UVM Simulation Acceleration in FPGA Prototyping Board
Session 06: CyberWorkBench: High Level Synthesis with NEC
Session 07: Ask Aldec: Demos, Roadmaps, Partners, Q&A, etc. 
Session 08: OSVVM for VHDL Testbenches

 

View complete Abstracts and Registration at www.aldec.com/dac2015.

 

Aldec Cocktail Reception

Monday, June 8 from 5:00pm to 6:00pm at Booth #1725

View a demo at the Aldec booth on Monday for free entry to our raffle drawing prize giveaway. Winners will be announced during the cocktail reception Monday evening.

 

About DAC

DAC is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP). www.dac.com

 

About Aldec

Established in 1984 and headquartered in Henderson, Nevada, Aldec, Inc. is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com