Aldec enhances ALINT-PRO-CDC with Advanced Violation Analysis Capabilities and an Extended Set of Dynamic Checks

Date: Aug 10, 2015
Type: Release

Henderson, NV – August 10, 2015 Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, announces the release of ALINT-PRO-CDCTM 2015.08. With this release, Aldec delivers comprehensive handshake synchronizers support, static checks for proper clock and reset generation, logic partitioning in the design hierarchy, and extended means for violations analysis.


“Continual improvement is the proper way to build a product,” said Pavlo Leshtaiev, Product Manager, Aldec Software Division, “Based on feedback from our customers and the continuous work of our development team, Aldec has delivered an even more reliable tool. This release offers an extended set of dynamic and static checks which helps create safe CDC code with minimum delays and the best possible quality.”


ALINT-PRO-CDC offers numerous functional improvements as well as usability and performance upgrades. Most notable items are:


Static Verification Rules The ALDEC_CDC plug-in is extended with 10 new rules. These rules are focused on creating clean design hierarchy with all clock and reset generation logic located in the dedicated instances. This allows convenient design constraints specification and reduces the probability of random logic being erroneously used as a clock.


Static Violations Analysis Usability of Schematic Viewer is improved with added capability to highlight all netlist elements with a distinct color based on the clock domains they belong to. Incremental mode is also supported in the Schematic Viewer. It is now possible to leave only selected elements on the scheme and interactively add connected elements to it.


Dynamic Verification The set of dynamic checks is extended with assertions and coverage for EN-based and handshake synchronizers, metastability emulation is generated for reset synchronizers. VHDL is now supported as a target language of the generated testbench (see Release Notes for limitations).


Design Constraints Support Virtual clocks are now supported, resulting in more accurate violations for properly described design top-level interface.



ALINT-PRO-CDC 2015.08 is available today. For additional information or to request a free evaluation download, visit


About Aldec

Aldec Inc., established in 1984 and headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

Media Contact: Aldec, Inc.                               
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400
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