Say Hi To Hybrid: ARM Fast Models meet Aldec Emulation

Date: Oct 29, 2015
Type: In the News

by Doug Amos

It has been proposed for some time that virtual platforms could be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. However, that proposal now has evolved into hybrid emulation, a practical solution to allow pre-silicon verification and validation of today’s complex SoC designs.

First-rate work by the standards body Accellera and the Open SystemC Initiative (OSCI) has given us all Transaction-Level Modeling, or TLM. TLM has enabled us to create a virtual platform of a CPU sub-system, trading off accuracy for speed in order to provide an early target to test software. In the early days, a common obstacle to realizing such virtual platforms was the availability of SystemC models for various components, for example, a new CPU. If none was available then we would lose time generating a trustworthy model, eroding the benefit of early software test.

For the rest of this article, visit Semiconductor Engineering.

Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.