Aldec to Offer Complete Coverage Analysis with the Addition of Condition and Path Coverage to Active-HDL’s Powerful Coverage Database

Date: Mar 16, 2016
Type: Release

Henderson, NV – March 16th, 2016 – Aldec, Inc., today announces the latest release of its mixed-language, FPGA Design & Simulation Platform, Active-HDL™ 10.3. Active-HDL, which has long supported numerous code coverage types, now delivers a complete coverage analysis package for FPGA and ASIC designers with the addition of Condition and Path Coverage to its powerful ACDB coverage database.


Coverage analysis is a popular debugging mechanism for reducing a verification time. This step traces code execution and delivers information that directly improves the quality of verification by measuring the amount of code that has been exercised while identifying areas that have not tested well. The coverage analysis tools in Active-HDL are completely automated and require no user intervention or changes to the design or testbench.


“Complete coverage analysis is now possible with the addition of Condition and Path Coverage support to Active-HDL,” said Satyam Jani, Active-HDL Product Manager. “Conditional statements such as if-else and case create various paths in the design that divert the stimulus flow in a specific path. Path coverage enhances the analysis of statement/branch coverage by providing information on completeness of program execution paths. Similarly condition coverage enhances expression coverage data by monitoring and factorizing logical expression used in conditional statements.”


About Active-HDL

Active-HDL™ is an FGPA veteran tool that has been helping FPGA designers for more than 15 years. It is an HDL-based FPGA Design and Simulation solution that supports the newest FPGA devices available from all leading FPGA vendors. The high-performance, mixed-language simulation solution interfaces with nearly one hundred twenty (120) third party vendor tools and provides FPGA designers a single platform that can be used independently of the targeted FPGA design flow. Active-HDL 10.3 supports design creation and simulation of the newest industry-leading FPGA devices from Altera®, Lattice®, Microsemi™ (Actel), and Xilinx®.


The 10.3 release of Active-HDL also includes numerous new features, enhancements, and performance optimizations. For additional information, tutorials, free evaluation download and What’s New Presentation, visit


About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

Media Contact: Aldec, Inc.                               
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400
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