Semiconductor Engineering: Too Big To Simulate?

Date: Oct 27, 2016
Type: In the News

By Ann Steffora Mutschler

“Simulation time also depends on the description abstraction level,” said Zibi Zalewski, general manager of the Hardware Division at Aldec. “RTL-behavioral (synthesizable) will simulate faster than structural gate level. Functionally control logic/FSM will simulate faster than computation intensive data paths (DSPs).”

As such, simulators for big projects are commonly used for module and IP level verification, while hardware verification methodologies are covering SoC system level. But today, even sub-systems are becoming very advanced units that cause the simulation to take a day or longer, complicated by the fact that the scope of testing is increasing too, he said. And while UVM verification, which has become a standard for big ASIC and FPGA projects, is a great tool in the verification engineer hands, it requires significant simulation power.

Fortunately, there are multiple options available in case simulation becomes a bottleneck because of design and testing environment complexity... 

This is an excerpt of an article that appeared on Semiconductor Engineering.

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