Top Aldec Design and Verification Blog Articles from 2016

Henderson, NV – December 7, 2016 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for SoC and ASIC designs, publishes a regular Design and Verification Blog covering news, popular methodologies, and helpful tips and features authored by our top engineers and guest authors. Below are some of our top-viewed articles from 2016.

	FPGAs Accelerating IoT Gateway and Infrastructure Tiers   Exciting times as Aldec uses 30 years of FPGA expertise in new ways
	UVM. It’s Organized and Systematic.   Mastering the fundamentals
	Aldec Verification Tools Implement the ASIC Verification Flow   Insights from Dr. Stanley Hyduke, Aldec Founder and CEO
	Why I see C in SCE-MI   A Hardware Emulation Guide for Non-C Designers
	The UVM Configuration Database   Keeping a neat repository for flexible testbench structure
	Introduction to AXI Protocol   Understanding the AXI interface
	To Emulate or Prototype?   Is it even a question?

For more on Aldec’s helpful solutions, visit www.aldec.com/solutions or email sales@aldec.com.

About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Emulation, Design Rule Checking, Clock Domain Crossing, VIP Transactors, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com