Aldec continues to stack up pre-compiled verification libraries and delivers significant SystemVerilog and UVM speedup with latest release of Riviera-PRO

Date: Apr 11, 2017
Type: Release

Henderson, NV – April 11, 2017 – Aldec, Inc., today announced the latest release of Riviera-PRO™ 2017.02 - Advanced Verification Platform, with new functionalities and libraries aimed at verifying complex System-on-Chip (SoC), ASIC and FPGA designs. This new release of Riviera-PRO brings significant performance improvements in SystemVerilog and UVM compilation and simulation. SystemVerilog random constraint simulation is now 28% faster, UVM simulation is 10% faster, and designs using VHPI interface simulate 3800% faster.


The open-source Universal VHDL Verification Methodology (UVVM) joins widely-used industry verification libraries OVM, UVM, OSVVM as pre-compiled libraries in the latest Riviera-PRO. UVVM is a powerful framework and methodology, together with OSVVM randomization and UCIS based functional coverage delivers an effective reusable solution for system level designs.


“A robust portfolio of ready-to-use verification libraries, together with full support for Metric Driven Verification offers our users a fast and reusable solution to verify complex SoCs and FPGAs,” said Radek Nawrot, Riviera-PRO Product Manager. “Each universal verification library offers a unique capability, that’s why we are happy to deliver multiple pre-compiled verification libraries to provide our users the option to choose the libraries best-suited to address their own verification challenges.”


Riviera-PRO 2017.02 also introduces a larg­e number of enhancements in coverage viewers to better align visualization of data to the needs of the user.


The 2017.02 release of Riviera-PRO also includes numerous new features, enhancements, and performance optimizations. For additional information, tutorials, free evaluation download, Overview and What’s New Presentations, visit


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.

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