Aldec @ DVCon India 2017 - accelerating SoC validation by extending QEMU open-source capabilities

Date: Sep 12, 2017
Type: Release

Bengaluru, India – September 12, 2017 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, extends QEMU™ open-source emulator capabilities with hardware-assisted co-emulation at DVCon India Conference and Exhibition to be held on September 14-15, 2017, in Bengaluru, India.


QEMU is a popular open-source virtual machine emulator that provides instruction-accurate executions of software. QEMU users are able to emulate software apps and drivers on the virtual machine to discover generic software bugs early in the project cycle without the need for the final RTL IPs, but they can overlook low-level hardware dependencies in QEMU-only environment.


 “We have developed the required SCE-MI/TLM and TLM/QEMU bridges to connect QEMU and HES Emulator to provide better performance and RTL debugging capability at the SoC level, said Louie De Luna, Director of Marketing. “This hardware-assisted approach guarantees thorough and comprehensive SoC validation for both production software and RTL without the need for dummy patches,” he added.


Such a hybrid co-emulation platform accelerates the verification process, and delivers a testing platform for hardware and software teams before the SoC RTL is complete and ready for prototyping, another ‘shift-left’ verification approach that boosts productivity.

soc validation

See Aldec’s Verification Spectrum in action @ Booth#105:

  • Simulation - Advanced Mixed-Language Simulator with UVM Support
  • DRC/CDC Analysis- Single platform for Design Rule Checking (DRC) and Clock Domain Crossing (CDC) verification methodologies, with SystemVerilog design rules
  • Emulation - Hardware-assisted co-emulation with QEMU, booting LINUX OS and running image filtering application
  • Physical Prototyping – Multi-FPGA design partitioning technology


About Hardware-Assisted Co-emulation with QEMU and HES Platform

A reliable HW/SW co-verification technique is indispensable for SoC validation. QEMU is a generic and open source machine emulator that supports various computer hardware architectures including ARM® Cortex® families, and can be connected with the Aldec HES™ emulation platform to provide a complete hybrid co-emulation environment for SoC designs.


HES emulation platform can emulate any part of a design written in synthesizable SystemVerilog or VHDL, most often a custom designed, in-house SoC subsystem implementing unique features of a given SoC. A general purpose processor subsystem (CPU) is often acquired from a third-party vendor as hard IP or netlist file without RTL code being available. QEMU is used to emulate standard components such as this and to run embedded firmware and software tests. It can now be easily connected with the HES-emulation platform, enabling all SoC subsystems to be verified together.


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solutions and Military/Aerospace solutions.

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