Aldec to Present Software Driven Test of FPGA Prototype @ DVCon Europe 2017 Date: Oct 9, 2017 Type: ReleaseMunich, Germany – October 9, 2017 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, will present “Tutorial: Software Driven Test of FPGA Prototype” at the DVCon Europe Conference and Exhibition to be held on October 16 – 17, 2017 in Munich, Germany. Tutorial: Software Driven Test of FPGA Prototype Schedule: Monday, October 16, 2:00PM-3:30PM, Forum 7 Speakers: Krzysztof Szczur, Aldec Inc. and Radosław Nawrot, Aldec Inc. Abstract: Recent evolutions of FPGA technology follows the SoC path known from ASIC designs. We now have hybrid devices such as Xilinx® Zynq™ that combines ARM Cortex with reconfigurable FPGA within a single chip. These devices are flexible enough to be used as embedded software driven testbench for the design prototyped in FPGA. Limited FPGA capacity of Zynq-like devices is not an obstacle in this regard because additional high capacity FPGA parts can be added to the FPGA board such as the Xilinx UltraScale (XCVU440) that provides an estimated 26 Million ASIC gates. In this tutorial, we will explain how to build a robust embedded testbench that runs software driven test scenarios. The tutorial will present multiple connectivity options applicable for SoC testing including AMBA AXI Interconnect and demonstrate an example with Aldec’s Proto-AXI interface and HES-US-440 prototyping board containing both Virtex Ultrascale XCVU440 for the design and Zynq XC7Z100 for the embedded software driven testbench. See Aldec’s Verification Spectrum in action @ Booth#404: Simulation - Advanced Mixed-Language Simulator with UVM Support DRC/CDC Analysis- Single platform for Design Rule Checking (DRC) and Clock Domain Crossing (CDC) verification methodologies, with SystemVerilog design rules Emulation – Hardware Assisted: In-Circuit Emulation, Co-Emulation with Virtual Prototypes, UVM Simulation Acceleration Physical Prototyping – SoC, ASIC & ASSP Prototyping in FPGA with multi-FPGA design partitioning technology About Aldec Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solutions and Military/Aerospace solutions. www.aldec.com
