Aldec to showcase FPGA-based algorithm accelerators at SC17

Denver, CO – November 9, 2017 – Aldec Inc., unveils FPGA-based accelerators, HES-HPC™ at SC17 to be held on November 12-16, 2017 in Denver Colorado.  Utilizing the latest and most powerful Xilinx® UltraScale™ and UltraScale+™ devices with the highest DSP slices, the accelerators are ideal for on premise environments running low-latency applications and algorithms used in Genome Short Reads Alignment, Cloud Computing, Data Mining, High-Frequency Trading and Encryption Code Breaking. 

The scalable HES-HPC platforms support PCIe x8 / PCIe x16, include on-board memories, and available in multiple configurations including:

• 1U or 2U rack built with 7x low profile, PCIe x16 cards with UltraScale+ XCVU9P (~2.5M Logic Cells, 6,840 DSPs), 3x QDR-II+ 144Mb memory, 2x QSFP28 connectors up to 131 Gb/s
• Desktop System with 1x UltraScale Kintex XCKU115 (~1.5M Logic Cells, 5,520 DSPs) connected to 1x Zynq XC7Z100 as host,  2x 16GB DDR4, 4x 576Mb RLDRAM-3, 2x QSFP+ connectors, USB3.0
• Single Board with 1x UltraScale Virtex XCVU440 connected to  1x Zynq XC7Z100 as host, 2x 16GB DDR4 and 2x 576Mb RLDRAM-3 memories, 4x FMC and 1x QSFP+ connectors.  

“In order to ease the host-to-FPGA transmission, we provide the PCIe-to-AXI hardware infrastructure and C/C++ software API with link speed of 2+GB/s, and it can be used when writing high-level applications for Linux or Windows.” said Louie De Luna, Director of Marketing. “We also provide the Hes.Asic.Proto software package with necessary drivers and utilities for programming and communication with the board.”

Aldec Demonstrations @ Booth#254:

• Design Encryption Standard (DES) Code Breaker - a reference design for DES Brute Force Code Breaker with a total key combination of 2^56, max input clock frequency 175MHz and 175M combinations/sec for 1 DES instance. The total hack time for 6144 DES instances is ~20h using HES-HPC with 6 Xilinx UltraScale US-440 chips.
• Vibe Motion Detection – a reference design based on ViBe™ Background Subtraction algorithm and HES-HPC™ FPGA-based Accelerator running @1920x1080, 30fps. The image processing background subtraction techniques are utilized to transform and detect moving objects in recorded video. HES-HPC platform provides performance enhancement by utilizing extreme parallel processing capabilities of FPGAs to execute computationally intensive image transformations.
• Genome Short Reads Alignment - a high-performance reconfigurable FPGA accelerator engine for Renelife® ReneGENE™, offered on HES-HPC for accurate, and ultra-fast big data mapping and alignment of DNA short-reads from the Next Generation Sequencing (NGS) platforms. AccuRA demonstrates a speedup of over ~ 1500+ x compared to standard heuristic aligners in the market like BFAST which was run on an 8-core 3.5 GHz AMD® FX™ processor with a system memory of 16 GB.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Embedded, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com