Aldec presents ‘Dealing with CDC verification complexity in large-scale FPGA designs’ at FPGA Forum 2018

Date: Feb 8, 2018
Type: Release

Trondheim, Norway – February 8, 2018 - Aldec joins ARM, Intel, Thales and other top tier exhibitors at The 13th FPGA Forum that runs February 13-15, 2018 in Trondheim, Norway, and provides a forum for the exchange of new knowledge in FPGA design and verification methodologies and best-practices.


The conference will showcase leading research in the form of technical papers and tutorials. Taking part in the conference presentations, Sergei Zaychenko, Aldec Software Product Manager presents ‘Dealing with CDC verification complexity in large-scale FPGA designs’.



The number of interacting asynchronous clock domains has grown significantly over the last years in FPGA projects. Achieving CDC sign-off is equally important in today's FPGA designs as functional correctness, timing closure, power reduction, reaching optimal resource utilization. The existing dominating CDC verification methods and tools were designed mainly for the ASIC flow, and must be modified to be efficient in the context of FPGA. So what exactly is expected to be provided by a CDC tool for FPGA market?

First of all, a correct interpretation of the built-in primitive libraries is a must, especially the clocking resources, memories, and serial I/O blocks. Most often, the provided simulation models aren't useful for CDC analysis, and cannot be synthesized directly. Some of the cells, however, have very complex timing expectations with multiple clocking and resetting modes, heavily dependent on generics. Second, the issues at the boundary with the IP blocks, mostly available in the encrypted form only without the detailed timing constraints. Then comes the really advanced issues involving multiple dynamically switchable clock modes, exclusive clock groups, and reconfigurable design partitions, which dramatically increase the complexity of CDC verification. Manually describing all the tiniest timing properties of each cell in each mode is way too error-prone, and the tools must help with that. Some of the CDC solution patterns invented for ASIC need to be modified for FPGA to overcome differences in synthesis and technology mapping steps.  Another obstacle to deal with during the CDC sign-off is associated with preparing the correct timing constraints, as well as CDC-specific placement hints. A good CDC tool can help to generate the initial draft based on the topology, as well as check the existing constraints set for consistency and completeness. One of the biggest challenges is achieving the portability between vendor-specific SDC extensions. Finally, it is expected to have a straightforward interoperability between the tools for synthesis & implementation, CDC design rule checks, and functional CDC-aware simulation.


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, SoC and ASIC Emulation/Prototyping, Design Rule Checking, CDC/RDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solution, High-Performance Computing and Military/Aerospace solutions.

Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.