VHDL 2018 Support & Enhanced Automation - Aldec adds VHDL Standard 1076-2018 extensions and automatic coverage model generation to Riviera-PRO™

Date: Nov 13, 2018
Type: Release

Henderson, NV – November 13th, 2018 – Aldec, Inc., an industry leader in electronic design verification, has added VHDL-2018 interfaces and automatic coverage model generation to its Riviera-PRO™ advanced verification platform.


This early support for VHDL Standard 1076-2018 includes conditional compilations, conditional expressions in declarations, constraint inferral (from initial values), and bidirectional connections.


“Aldec continues to actively support industry-based initiatives related to hardware description languages,” comments Radek Nawrot, Director of Operations at Aldec. “We believe we’re one of the first EDA companies to officially offer support for VHDL-2018, certainly within the growing Open Source VHDL Verification Methodology, OSVVM, community.”


OSVVM is a comprehensive, advanced VHDL verification methodology. Like UVM, OSVVM is a library of free, open-source code (packages) used to implement functional coverage, constrained random tests, and intelligent coverage random tests with a conciseness, simplicity and capability that rivals other verification languages.


Regarding the automatic coverage model generation, it builds on the capabilities of Riviera-PRO’s UVM register generator; announced in May 2018. Nawrot continues: “The automation of coverage model generation not only saves a great deal of time, but it also removes the risk of mistakes being made when changes are made to the design structure.”


Both above additions to Riviera-PRO™ are in direct response to requests Aldec received from engineers at the 2018 Design Automation Conference in San Francisco.


“We pride ourselves on listening to customers and understanding what it is they need to make them more productive and to increase their confidence in their designs - two goals which are very much connected,” concludes Nawrot, “as opposed to telling people what they should be using. Aldec’s tools are designed by verification engineers for verification engineers.”



About Riviera-PRO™

Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. The tool enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Emulation/Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, High-Performance Computing and Military/Aerospace solutions. www.aldec.com

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