Aldec at SC19: Showcasing Multi-FPGA Partitioning Software for Multi-FPGA-based Algorithm Accelerators

Denver, CO, USA – November 18, 2019, Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for SoC and FPGA designs, is exhibiting at Supercomputing19 to be held on November 18-21, 2019 in Denver, Colorado, and will be demonstrating a powerful multi-FPGA partitioning software for multi-FPGA-based algorithm accelerators.

“We will showcase the recently introduced automatic FPGA partitioning feature of our popular HES-DVM™ tool, our fully automated and scalable hybrid verification environment for large SoC designs,” said Louie De Luna, Director of Marketing. “Manual partitioning of designs with multiple FPGAs, can take days or even weeks, whereas HES-DVM can perform the task in minutes.”

The partitioning software can be used with Aldec’s HES Prototyping boards and as well as 3^rd party prototyping boards.

See the Aldec demos at SC19, Booth#228

• DNN-based Traffic Detection Using Xilinx Zynq US+ FPGA– In this demo, traffic detection is done using a Convolutional Neural Network (CNN) on a TySOM-3A-ZU19EG development board. Deep Learning Processing Units (DPUs) are implemented in the FPGA for the acceleration of object detection and recognition, which results in 45fps for three input channels.
• Vibe Motion Detection – a reference design based on ViBe™ Background Subtraction algorithm and HES-HPC™ FPGA-based Accelerator running @1920x1080, 30fps. The image processing background subtraction techniques are utilized to transform and detect moving objects in recorded video. HES-HPC platform provides performance enhancement by utilizing extreme parallel processing capabilities of FPGAs to execute computationally intensive image transformations.
• Automatic Partitioning Design for Multi-FPGA Prototyping - Multi-FPGA partitioning has always been a challenge due to the limited number of FPGA I/Os and FPGA-specific clocking trees. Aldec provides a HES-DVM prototyping toolbox that automates design partitioning for multiple FPGAs and integrates an ultra-fast HES Proto-AXI host bridge.

About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com