Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-In

Date: Mar 4, 2021
Type: Release

Henderson, NV, USA – March 4, 2021 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added more than 60 new HDL rules to ALINT-PRO™’s DO-254 rules plug-in and has made several enhancements to the tool’s Design Entry capabilities to boost productivity.


The new rules (62 in total) join the 97 already present in the tool’s DO-254 plug-in, and help engineers using complex hardware devices, such as FPGAs, meet specific DO-254 process objectives to receive overall system approval.


Certification authorities recommend that applicants define and follow HDL coding standards commensurate to the complexity of the FPGA design. Adhering to HDL coding standards enforces industry best-practices and techniques to ensure high-reliability designs, prevent design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.


Janusz Kitel, DO-254 Program Manager at Aldec, comments: “Unfortunately, DO-254 does not define the coding standard. This makes applicants feel uncertain in defining the proper one, especially for organizations new to DO-254. ALINT-PRO provides a comprehensive ruleset based on the best practices guidelines and experience from the industry.”


Kitel goes on say that the expansion of ALINT-PRO’s ruleset comes at a good time for users, as a new guidance of Development Assurance for Airborne Electronic Hardware has been released. The AMC 20-152A document - already released by the EASA and harmonized with incoming FAA AC 20-152A – recommends applicants follow hardware design standards for Design Assurance Level (DAL) C projects, while previously it was required only for the most safety critical DAL A and B projects.


Kitel: “More designs for airborne applications will now need to define and follow an HDL coding standard, and ALINT-PRO – with its tool qualification package, used to prove the tool is capable of enforcing the coding standard automatically – can provide the necessary assurances and save engineers a great deal of time.”


As for the Design Entry enhancements to ALINT-PRO - enhancements that will benefit all users, whether using the DO-254 rule plug-ins or not – these include:

  • Optimized RAM/ROM extraction has reduced synthesis phase memory consumption;
  • Subprogram body checking is now supported by a number of RTL-based checkers and by an FSM extraction algorithm;
  • The conversion of cores containing protected IP has been improved; and
  • There is a new mechanism of CDC Assertions generation that allows users to extract the assertions through the inclusion of just one line of code (a project.generate.assertions command) in their testbench.


Alex Gnusin, ALINT-PRO Product Manager, comments: “The performance enhancements we’re continually making, along with our regular introduction of evolving best-practice rules and how we’re on top of changes taking place in our fast-paced industry, make ALINT-PRO the tool of choice for finding bugs early on in your design flow and demonstrating compliance where and when required.”


ALINT-PRO 2021.02 is now available for download and evaluation.



ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, avoiding problems on further design stages, clocks and reset tree issues, CDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically.


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.

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