Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCs

Versal ACAP, developed by Xilinx/AMD, is a groundbreaking adaptable platform comprising an AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC) and hardened domain-specific IPs. Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between AIE, PS, and PL. The entire hardware emulation setup and system integration is done within the Vitis environment. Vitis runs the AIE simulator for the graph application, the Riviera-PRO simulator for the PL kernels, and QEMU (open-source system emulator) for the PS host application. SystemC models are also available for the AIE and NoC, and they can be simulated in Riviera-PRO too. System simulation is highly critical for any Versal ACAP design because of its complex adaptable architecture and high-logic density. The full system design can be tested with full debug visibility much earlier in the project cycle without any physical hardware, making it easier to run more test scenarios, test corner cases, and debug complex problems.

UVM is a versatile verification methodology that enables users to run advanced verification flows for large scale FPGAs and SoC FPGAs. However, because of its advanced nature, writing UVM from scratch can be a complex and tedious task. Riviera-PRO’s new UVM Generator feature alleviates some of the complexity by automatically creating the UVM testbench for any given design under test written in VHDL or Verilog. It also creates a basic framework of the UVM environment with all its components. Along with SystemVerilog source files, the UVM Generator automatically creates the TCL macros for controlling the simulation process. In this presentation we will be using an MPSoC reference design generated from Vivado as the design under test for the generated UVM environment.

This presentation showcases the simulation of the Ibex core, a small and efficient 2-stage in-order 32b RISC-V processor core. The simulation of the SV/UVM testbench for verification of the Ibex core uses Riviera-PRO. This SV/UVM testbench uses the open source RISCV-DV random instruction generator, which generates compiled instruction binaries. We then load these binaries into a simple memory model which then stimulates the Ibex core in Riviera-PRO to run this program in that memory. We then compare the Ibex core simulation trace log against a golden model generated by an Instruction Set Simulator (ISS) trace log to check for correctness of execution. The testbench is created based on its usage of the RISCV-DV random instruction generator developed by Google.

VHDL-2019 is the latest iteration of the IEEE 1076 Standard. This version was heavily influenced by the VHDL users rather than the EDA vendors. Language changes were driven by the use cases. These changes had multiple opportunities to be pruned from implementation. Firstly, the new feature was discussed and then these features were then voted on and ranked. Among the high ranked features, some were chosen by volunteers to draw up proposals. Proposals were required to provide use models. Proposals were then developed into language change specifications (LCS). The entire process was driven by volunteers, and almost all were users. In this presentation we will explore the new VHDL 2019 features such as interfaces, conditional analysis, file IO, protected types enhancements & data structures, and several enhancements to RTL and testbench coding capabilities.

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies FPGA/ASIC verification projects from start to finish. Aldec’s new OSVVM testbench generator automatically generates testbench code that includes libraries, components, sources, connections and scripts for automation. Users can generate a very simple OSVVM test and complex OSVVM environment with multiple verification components (VC) and TestCtrl units. 

Assertion-based verification (ABV) is the use of assertions for the efficient verification of low-level design specification. These assertions could be verified by simulation and formal verification methods. SystemVerilog Assertions (SVA) standard provides powerful means to express both immediate and concurrent assertions as well as functional coverage constructs. Unlike SystemVerilog, VHDL does not include the concept of concurrent assertions (while VHDL assert statements being similar to immediate assertions in SVA). In this presentation, we will present various methods to implement assertions in VHDL designs as well as identify the strengths and limitations of each method. These methods include PSL (VHDL flavor), the usage of Open Verification Library (OVL) as well as concurrent assertions development using procedural code with assert statements.

This interface developed by Aldec is intended to interact with HDL design and simulation process directly from Python language. The minimal installation requirements using only one binary linkage library makes it easy for the users to install and start using. It is placed on Python search path granting a user access to the simulator and simulated design. This interface supports execution of commands in the Active-HDL and returns its status. They can be passed in the interactive mode using command prompt conversation or used inside the code. Predefined methods help with automatically performing a sequence of operations, for example, complex operations like opening workspace, design or initializing simulation. The simulation process is controlled in a natural way using hierarchical naming concept of Python. HDL objects are created following the Python concepts of dynamic creation of objects. This approach eliminates an overhead connected with design scan and replication at startup on the Python side. To maintain the modeling concurrency, the callbacks mechanism is provided for signal changes and elapsing of time. All above functionalities can be used in an interactive mode directly from Python prompt.

Cocotb is a CO-routine based CO-simulation Testbench environment for verifying VHDL/Verilog RTL using Python. It uses the same design-reuse and functional verification concepts like UVM, however is implemented in Python. In this presentation, we will introduce Cocotb, and will outline how Cocotb can provide significant savings in development time, promote code re-use and ultimately reduce project time-to-market and total development cost. It allows developers to start with small, directed testbenches, and evolve them into more thorough constraint-random tests.

Today's designs widely use different types of bus interconnects for both external and internal (IP-level) communication. The new ALINT-PRO functionality allows designers to extract, review and verify the correctness of bus interface connections. In addition, ALINT-PRO is capable of automatically connecting bus protocol checkers & monitors to current design to enable functional verification of the bus interfaces in simulations.

Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code, and therefore are excluded from advanced linting. In fact, this is a correct approach as hard IP blocks are assumed to be functionally stable and may be excluded from both static and dynamic verification. However, clock domain crossing verification still requires hard IP block constraining. In most cases, these IP-level constraints are not complete and require special attention from designers, as the top-level CDC analysis relies on the quality and completeness of hard IP constraints. In this presentation, we will present a robust hard IP design constraints development methodology. This methodology is illustrated for different IP block types and on the number of FPGA designs.

Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other, and still be expected to work reliably. Xilinx Parameterized Macros (XPM) can be used to implement CDC, FIFO and BRAM solutions in FPGA designs. XPM usage enables safe cross-clock domain transfers for control signals and data buses, providing seven clock domain crossing (CDC) capabilities such as single-bit, pulse, gray-code or handshake synchronizers. Also, Xilinx Vivado provides a CDC checker, reporting paths that start in one clock domain and pass into another. However, the capabilities of Vivado CDC checker are limited compared to advanced CDC analysis tools, while rigorous CDC verification is essential for safety and functional reliability of FPGA designs. In this presentation, we will present the methodology and design examples of efficient CDC verification for designs containing Xilinx Parametric Macros.

The use of advanced verification tools can significantly reduce the number of non-trivial bugs, save engineering time and resources and, more importantly, increase the reliability of FPGA designs. Static design verification is an essential part of a robust verification process that includes advanced linting and Clock Domain Crossing (CDC) analysis. In this presentation, we will provide a methodology overview of advanced linting and CDC analysis, demystify the type of design problems they solve and show how they can be added to the Microchip Libero® tool flow. We will then show a working example of how these methods can be applied to Microchip PolarFire® SoC FPGA Icicle designs. Starting from Libero IDE, we will show automated project conversion into the ALINT-PRO environment for advanced linting, block and top-level constraints development and CDC analysis.

HDL co-simulation with various domain-specific frameworks is critical for enabling heterogeneous computing with FPGAs. In this presentation, we will show a standardized co-simulation interface between GNURadio and Riviera-PRO. GNURadio is an open-source software development toolkit that provides signal processing blocks to implement software-defined radios (SDR). Advanced signal generation, configuration, processing, viewers are available in GNURadio including filters, channel codes, synchronization elements, equalizers, demodulators, vocoders, or decoders. Functions/algorithms that need acceleration are implemented in HDL and synthesized into FPGAs. GNURadio users create flowgraphs/project for the desired SDR.

The use of high-speed interfaces such as PCIe and Ethernet is becoming popular within avionics systems. However, the verification of such designs for DO-254 compliance with design assurance level (DAL) A or B is problematic. FPGA designs that use asynchronous clocks with multiple high-speed serial interfaces produce non-deterministic results during physical tests. Simulation results are optimized because they are based on simplified models, while the test results in physical hardware depend on the phases of clock oscillators. Bit-level verification struggles with this, especially when comparing physical test results against simulation results for traceability, and many false errors are likely to be observed. In this webinar we will introduce transaction-level methodology (TLM), and how it can be used for verifying PCIe-based FPGA designs for DO-254 compliance. Transactions are easier to manage and correlate with the simulation results, therefore traceability is much easier to establish. Also, the untimed testbenches used with TLM are not sensitive to clock frequency and phase changes, which is ideal for verifying PCIe-based FPGA designs with non-deterministic behavior.

In today's fast-paced technological world, fabless design companies face enormous challenges in developing highly complex systems on chip (SoC). To ensure the reliability and correctness of SoC designs, a comprehensive pre-silicon verification approach is required. In this presentation, we will demonstrate how FPGA-based emulation cuts HDL simulation times enabling more robust test scenarios to be executed within designated verification schedule. Therefore, we will demonstrate Aldec HES-DVM, which is a universal platform that can be used for simulation acceleration, emulation and physical prototyping depending on the design phase. The core of the platform are the HES boards, the state-of-the-art FPGA-based prototyping boards, aided with DVM software to enable verification with hardware in the loop throughout the whole verification cycle. Finally, we will present a case study that shows the effectiveness of the emulation technique. The case study involves the verification of a SoC design using the RISC-V processor architecture. We’ll also demonstrate the architecture of the testbench based on SCE-MI interface that allows for seamless use of either simulation or emulation techniques.

HES-SyntHESer is an advanced logic synthesis tool designed for mapping large RTL designs to AMD and Intel FPGAs optimized in terms of synthesis time and usage of hardware resources. SyntHESer is also able to synthesize designs to technologically independent (GARCH) netlist with general low-level cells enabling the mapping to different FPGA vendors and technologies. SyntHESer supports all VHDL and Verilog standards, including SystemVerilog and VHDL2008 as well as mixed languages.