MathWorks Simulink®Category : Co-Simulation InterfacesThe Simulink Interface simplifies verification of hardware designs by providing robust visualization and analysis toolsets. It allows co-simulation of mathematical and hardware components of system-level design, and gives flexibility of successive replacement of mathematical models describing the system with their target HDL equivalents. You can co-simulate functional blocks described by using mathematical formulas and VHDL entities, Verilog modules, and EDIF cells that are used as black-boxes during the verification process performed within the Simulink environment. The Simulink Interface offers the following benefits: Intuitive interface that fills the gap between HDL simulation and high level mathematical modeling environment for DSP systems. Displaying simulation results in both the Simulink environment and the Active-HDL Standard or Accelerated Waveform Viewer. Automatic value conversion between Active-HDL and Simulink. Advanced testbenches employing complex mathematical formulas used to stimulate unit under test (UUT). Integration with Synplicity Synplify DSP™ 6. Integration with Xilinx System Generator™
