SystemVerilog IEEE 1800™ (2005, 2009, 2012, 2017 and 2023) - DesignCategory : Supported StandardsSystemVerilog is a set of extensions to the Verilog HDL that allow a higher level of modeling and efficient verification of large digital systems. Originally developed by Accellera, SystemVerilog was standardized as IEEE Std. 1800™-2012. Riviera-PRO supports SystemVerilog IEEE Std 1800™-2005, IEEE Std 1800™-2009, IEEE Std 1800™-2012, IEEE Std 1800™-2017, and IEEE Std 1800™-2023 in three areas: hardware description extensions, assertions, and advanced verification. The design portion of the standard includes mainly synthesizable constructs and the constructs for behavioral modeling.
