Riviera-PRO EDU Configurations

Simulation of netlist in EDIF 2 0 0 format is supported by most Aldec Simulators. More   

SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems. More   

ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes. More   

ALDEC simulators provide comprehensive support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard. More   

Mixed Language More   

The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism to access and modify data in a simulated Verilog model. More   

VHDL/Verilog Synplicity Compatible Encryption More   

Accelerated Waveform Viewer (ASDB) More   

Simulations can be stopped on a breakpoint. Aldec supports both breakpoints in the source code as well as signal breakpoints. More   

HDL and Text Editor More   

Stepping through source code is one of the most common debugging procedures. Stepping is executing code one line at a time More   

Language Assistant with Templates and Auto-complete More   

The network floating configuration (multiple users) is based on a license started on a remote machine (license server) running on the Windows or Linux platform. More