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Title: Transaction Level Co-Emulation with Virtual Platforms

Description: Co-Webinar with Imperas® Abstract: Virtual platforms play a significant role in system level development, but require integration with ultra fast emulation systems for HW/SW co-verification. In this webinar we will introduce the new integration of Aldec's Transaction Level Emulation System with Imperas' OVPsim virtual platform simulator. Hardware and software design teams are now able to implement virtual models of processors, memory and peripheral modules while the RTL modules run in the emulator board. This integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.


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