Play WebinarTitle: OVM and UVM - Building a SystemVerilog Testbench in Riviera-PRODescription: Abstract: Aldec has recently added support for the Open Verification Methodology (OVM) for SystemVerilog, which is the basis of Accellera’s forthcoming standard Universal Verification Methodology (UVM). Resulting from years of experience within lead design verification teams and EDA companies, OVM provides common building blocks and predefined mechanisms for creating reusable and expandable test environments that take full advantage of SystemVerilog and SystemC verification capabilities. This webinar introduces basic OVM concepts and shows how users with different levels of experience can rely on OVM to quickly build up a layered, coverage driven, transaction-level verification environment which can be reused across different designs. These concepts apply equally well to UVM. Aldec provides a precompiled OVM library and a SystemVerilog compatible simulator to help customers take advantage of this latest design verification technology to meet the challenge of verifying today’s complex designs.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
