Play WebinarTitle: High-Performance PCIe 5.0 IP + VIP UVM Verification Environment Description: Together with Aldec, PLDA and Avery Design Systems, we will present and demo our newest PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA’s PCIE 5.0 XpressRich includes internal datapath automatic scaling, configurable pipelining, Rx stream mode for custom credit management, L1 PM substates, dynamically adjustable application clock frequency and clock/power gating. Avery’s APCIe-Xactor includes best-in-class Verification IP for PCIe GEN5, native SystemVerilog and UVM support, native randomization, layer wise protocol and debug tracker and 35+ callbacks for error injection. In Aldec’s Riviera-PRO you can run RTL simulation and debug, visualize simulation waveforms, view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections, and as well as use code coverage to analyze the efficiency of the UVM tests for exercising various parts of the RTL code.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
