Play WebinarTitle: VHDL-2019: Just the New StuffPart 2: Protected Types and Verification Data StructuresDescription: In this second webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL's protected type capabilities. Protected types simplify and abstract the construction of data structures. As such they are the enabling feature that makes it possible to create VHDL verification methodologies that are competitive with SystemVerilog + UVM, such as Open Source VHDL Verification Methodology (OSVVM). OSVVM uses protected types to create functional coverage, Intelligent Coverage random test generation, messaging (logs), unified error reporting (alerts/affirmations), and verification data structures (Memory Models, FIFOs, and Scoreboards). We will start the presentation with an overview of protected types and how they work. This will help all participants understand the impact of the changes. The balance of the presentation is dedicated to covering the changes and why they are important. Some of the updates discussed during this presentation will be: Protected Types with Generics Composites (arrays) of Protected Types Pointers to Protected Types Composition with Protected Types Protected Types on Entity Interface Protected Type Methods with File Types Protected Type Methods with Access Types Functions with Protected Type Parameters These new features allow libraries like OSVVM to take the next step in advancing VHDL’s verification capabilities.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
