Play WebinarTitle: VHDL-2019: Just the New Stuff Part 4: Testbench Enhancements Description: In this fourth webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL's Testbench coding capabilities. Many do not think of VHDL as a verification language, however, with the updates in VHDL-2002, 2008, and now in 2019, VHDL has increased its programming capability and is quite adept at creating good testbenches. Add to that methodologies and libraries such as Open Source VHDL Verification Methodology (OSVVM), and VHDL has become competitive with SystemVerilog+UVM. We have already covered some important items relevant to advanced VHDL testbench capability, such as Interfaces (Part 1), conditional analysis (Part 1), File IO (Part 1), and Protected Types (Part 2). This presentation furthers the discussion of Testbench enhancements and covers the following: Composites of File Types Functions with Access Type Parameters Functions with Out and InOut Parameters API for Assert Relax library requirements on configurations Map subprogram generics on call Report calling path of subprograms Garbage collectionSigning up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
