Play WebinarTitle: How to Simplify the Verification of Bus InterfacesDescription: Today’s FPGAs and SoC FPGAs use various types of bus interconnect - such as AXI, APB, AHB, Avalon or Wishbone - for both internal (IP-level) and external communication. A recently added feature to Aldec’s ALINT-PRO allows designers to extract, review and verify the correctness of bus interface connections. In addition, ALINT-PRO is capable of automatically connecting bus protocol checkers and can monitor the current design to enable functional interconnect verification in simulation. This webinar presents the bus interfaces extraction technology within ALINT-PRO. The concept of bus interface/interconnect instances will also be discussed. In addition, bus interfaces/interconnects visualization will be demonstrated with the new Interconnect Viewer and the enhanced Elaboration Viewer within ALINT-PRO. The automated process of “non-intrusive” protocol checkers and monitors attachment to design will be presented too.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
