Play WebinarTitle: Automating UVM flow using Riviera-PRO’s UVM GeneratorDescription: UVM is a versatile verification methodology that enables users to run advanced verification flows for large scale FPGAs and SoC FPGAs. However, because of its advanced nature, writing UVM from scratch can be a complex and tedious task. Riviera-PRO’s new UVM Generator feature alleviates some of the complexity by automatically creating the UVM testbench for any given design under test written in VHDL or Verilog. It also creates a basic framework of the UVM environment with all its components. Along with SystemVerilog source files, the UVM Generator automatically creates the TCL macros for controlling the simulation process. This webinar focuses on how to use UVM Generator and the benefits it brings to users creating UVM code from scratch. The UVM Generator creates the following components as part of the UVM testbench: Test, Virtual Sequences, Environment, Environment Configuration, Predictors, Scoreboards, Agents, Agent Configuration, Driver, Monitor, Coverage, SV interface, Sequence Items and Sequences. The generated UVM code can also be displayed in Riviera-PRO’s UVM Graph Window.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
