Play WebinarTitle: Running CDC Analysis with Xilinx Parameterized MacrosDescription: Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other, and still be expected to work reliably. Xilinx Parameterized Macros (XPM) can be used to implement CDC, FIFO and BRAM solutions in FPGA designs. XPM usage enables safe cross-clock domain transfers for control signals and data buses, providing seven clock domain crossing (CDC) capabilities such as single-bit, pulse, gray-code or handshake synchronizers. Also, Xilinx Vivado provides a CDC checker, reporting paths that start in one clock domain and pass into another. However, the capabilities of Vivado CDC checker are limited compared to advanced CDC analysis tools, while rigorous CDC verification is essential for safety and functional reliability of FPGA designs. In this webinar, we will present the methodology and design examples of efficient CDC verification for designs containing Xilinx Parametric Macros.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
