Fast Track™ to SystemVerilog for Verilog Users

Aldec’s Latest Free Online Training

Jerry Kaczynski, Research Engineer
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Many experienced Verilog users tend to ignore SystemVerilog - mainly because high-end verification features of the new language are getting the majority of the  attention in the press, and at conferences and trade shows. Those users may not realize that there are many SystemVerilog features that are very useful for them, no matter if they are writing synthesizable code or regular testbenches.

Fast Track™ to SystemVerilog for Verilog Users is a free, online training which assumes solid working knowledge of classic Verilog and shows all SystemVerilog enhancements that can be used in everyday coding. The first section of this training (suitable for all designers) is available now in Aldec’s Fast Track ONLINE™  training portal. The second section (coming soon) will provide gentle introduction to randomization, coverage, assertions, programs and similar advanced topics.


Fast Track ONLINE™ is available at no cost to all registered users and features a series of private, online training modules. Each module allows the user to go back to review material and ends with quick self-test before proceeding to ensure the material is grasped before proceeding.


Don't have an account? Signing up is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources.

In Sept. 2013, Aldec said goodbye to friend and colleague, Jerry Kaczynski. Jerry’s breadth of knowledge ran deep. He possessed over 20 years of experience in language and tool training, technical writing, and research engineering. Jerry held Bachelor and Master Degrees in Electronics from Warsaw University of Technology, Poland. He served his role as Aldec's Research Engineer with deep conviction, sharing his knowledge and research in the form of papers, articles, and trainings. He was an IEEE and Accellera committee member, and a staunch advocate for engineers through his involvement in the development of industry standards for VHDL, Verilog, PSL, SystemC & SystemVerilog.

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