Cocotb The COroutine based COsimulation TestBench (cocotb) is an extremely popular open-source and completely free environment for creating hardware testbenches in Python. These can be used to verify your design (written in VHDL or Verilog) using Active-HDL or Riviera-PRO. cocotb ensures your design and testbench interact seamlessly and provides you with a minimal yet helpful framework to access your full design in a true white box fashion. Much of the power of cocotb comes from its ecosystem. With half a million Python packages available, most problems - such as the parsing of file formats, interacting with other tools, or plotting the results – already have a ready-to-use solution. In addition, cocotb can be extended. Packages to perform constraint-random verification, functional coverage collection, or even an implementation of the UVM class hierarchy in Python are readily available. cocotb is vendor-neutral and driven by a globally distributed group of volunteers. If you find something in cocotb you’d like to see improved you’re welcome to join the community. With cocotb, writing testbenches for Verilog or VHDL design makes you productive, and is fun. Primary Use Case cocotb scales nicely, from designer simulations early in the design cycle to full-blown constraint-random testbenches. FPGA projects in particular benefit greatly from the rapid test setup and fast turnaround times provided by cocotb. Benefits cocotb is all about verification productivity. The verification is performed by software, and by writing code in Python you will have access to and benefit from everything that makes software development productive and enjoyable. cocotb allows you to focus on the verification task itself and stop fighting with language limitations. Why Python? It’s a very productive language. It’s easy interface between Python and other languages. There is a huge library of existing code, available for re-use. It is interpreted - tests can be edited and re-run without having to recompile the design. Python is popular - far more engineers know Python than SystemVerilog or VHDL. Webinar Video - Use Python and bring joy back to verification cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. cocotb encourages the same philosophy of design re-use and randomized testing as UVM, however is implemented in Python rather than SystemVerilog. With cocotb, VHDL/Verilog/SystemVerilog are normally only used for the design itself, not the testbench. In this webinar we will introduce cocotb and show how to get started with a small design using Aldec’s Riviera-PRO. We will also show a more complex example, giving you a taste how cocotb could add value -- and joy! -- to your next verification project. Webinar Recordings for cocotb Constraint Random Verification with Python and Cocotb Effective Testbench Creation Using Cocotb and Python Engineering best practices for Python-based testbenches with cocotb High-level thinking: Using Python for rapid verification of VHDL and Verilog designs Additional Links https://www.cocotb.org/ https://docs.cocotb.org/
