'Wireless Algorithm Validation’ with Aldec and Agilent

At the fast-approaching Design Automation Conference (DAC) 2013 in Austin, TX, Aldec will co-host an INSIGHT Session with Agilent Technologies on how to validate a digital signal processing algorithm for both floating and fixed point levels. As Riviera-PRO Product Manager, I will join Agilent Senior Product Marketing Engineer FAE, Sangkyo Shin, on Wednesday, June 5^th at 2pm in presenting a combined Agilent/Aldec FPGA flow that can be used to quickly validate communications digital signal processing (DSP) algorithms and accelerate physical layer (PHY) performance measurements.

Mr. Shin will review the system-level design challenges and how to solve them using the SystemVue™ software, which provides the capabilities needed to evaluate and design modern communication systems and related products. I will then take the auto-generated HDL code from a system-level concept down to HDL simulation in Aldec Riviera-PRO™ and FPGA implementation on Aldec HES-5™ hardware prototyping board. Attendees will gain valuable insight on the cross-domain approach to traditional FPGA design flow and learn how to validate FPGA design for leading edge wireless and radar system with a system-level simulation tool integrated into the traditional hardware design flow.

Here are some of the highlights we will review on the HDL/HW side:

• Using the Riviera-PRO / SystemVue HDL co-simulation interface you can simulate components represented in a hardware description language (HDL), VHDL and Verilog, in the same schematic with other SystemVue components.
  

• The ability to design all portions of a communications product in one integrated environment can eliminate design errors resulting from disconnects among design teams. By co-simulating with HDL designs, you can easily incorporate your existing HDL intellectual property into new designs, or co-simulate with SystemVue generated HDL.
• With HDL co-simulation, you can test hardware defined in HDL with a DSP algorithm, or use an algorithm written in HDL within an existing SystemVue design. This co-simulation capability in one design environment makes it easy to test HDL components along with other SystemVue design components and see the effect on the entire system.

• Hardware-in-loop (HIL) simulation leverages SystemVue FPGA design flow to generate HDL code, then implement it on the actual FPGA and co-simulate SystemVue and the design residing on Aldec hardware board. This achieves simulation acceleration, but also the most reliable verification of FPGA design - because the results come from the real FPGA.
• Agilent/Aldec HIL solution provides a number of important features such as the ability to use Riviera‑PRO’s HDL debugging tools with signals coming from real FPGA (preserved for debugging during design setup).

We will also benchmark HDL vs. HIL simulation and explain how to optimize your HDL design for efficient HIL simulation.

If you will be in attendance in Austin this year, join us for this complimentary session. INSIGHT Session are available at no extra cost to all attendees, guests, and staff members, simply select the appropriate session when registering for DAC.

You may also register for Technical Sessions and Demonstrations at Aldec’s Booth #2225. Learn more at www.aldec.com/dac2013.