Aldec Design and Verification Blog Trending Articles FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping Development of real-time SDR systems with Aldec HES Performing cross spectrum video processing on a TySOM-3 board How does the Mars Perseverance rover benefit from FPGAs as the main processing units? All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Development of real-time SDR systems with Aldec HES As telecommunication technologies evolve there is an on-going drive for the development of high-performance systems for radio communications. Part of that evolution involves implementing components in software functions that had traditionally been implemented in hardware.... Tags:Aceleration,FPGA,Hardware,HDL,Prototyping,Simulation,Xilinx,Design Like(8) Comments (7) Read more HW/SW Co-Simulation for SoC FPGA designs Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing system (PS) with state-of-the-art programmable logic (PL).... Tags:Co-simulation,Embedded,FPGA,Hardware,HDL,Simulation,SoC,Validation,Verification,Verilog,VHDL,Xilinx Like(2) Comments (0) Read more The Power of PCIe in Performance-based FPGA World Understanding High speed serial data transfer In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?... Tags:Aceleration,ASIC,Co-simulation,Documentation,Embedded,Emulation,FPGA,FPGA Simulation,Hardware,HDL,IP,Prototyping,Simulation,SoC,Validation,Verification,Xilinx Like(3) Comments (0) Read more Problems Accessing Registers? – See how UVM RAL can help. As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register can have several fields within it... Tags:ASIC,Debugging,FPGA,Simulation,SystemVerilog,UVM,Verification Like(2) Comments (0) Read more Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(4) Comments (0) Read more Do I really need a commercial simulator? A quick view of the benefits of a commercial simulator As an Applications Engineer I visit lots of potential customers, or talk to them at trade shows, who are doing FPGA designs but don’t own a commercial simulator. I ask them why that is. Most of the time it is budgetary restrictions. They don’t... Tags:Debugging,Design,Simulation,Verification Like(1) Comments (0) Read more SystemVerilog Functional Coverage in a Nutshell Use native SystemVerilog constructs as metrics for verification closure in Riviera-PRO Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly?... Tags:Simulation,SystemVerilog,Verification Like(1) Comments (0) Read more Trace Your Assertions When I enter the word “assertions” into a search engine I get lots of results, including articles, books, courses, and tools. Nothing unusual there, as assertions have been present in the EDA industry for many years. They considerably increase... Tags:Assertions,Debugging,Simulation,SystemVerilog Like(3) Comments (0) Read more Plots: A New Way To Analyze Data Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across... Tags:Co-simulation,Debugging,Hardware,Simulation,Verification Like(1) Comments (0) Read more Zynq-based Embedded Development Kit for University Programs Cost-effective solution for HW/SW development projects Creativity and innovation, which lead the society to success, rest on the foundational institutions such as schools and universities. They provide fertile soil to seed, grow and flourish enterprises.... Tags:Co-simulation,Embedded,FPGA,HDL,Prototyping,Simulation,SoC,university,Xilinx,Design,Digital Like(1) Comments (0) Read more
