How to Properly Verify Encrypted IP

FPGA vendors typically provide a set of various IPs which cannot be directly used for synthesis. Although these components are fully tested by the vendor, verifying the design that uses them can become a tricky task within some linting tools. The main obstacle being that the simulation models provided by the vendor, which again cannot be used for synthesis, leaving empty cells in the analyzed netlist.

Time-saving Block Level Design Constraints to the rescue

ALINT-PRO-CDC™ for Clock Domain Crossing Verification offers improved productivity and speed with comprehensive design constraints support, essential for proper clock domain verification. ALINT-PRO-CDC can read SDC files for design configuration and fills in the empty cells left in the analyzed netlist with the specialized model described with the Block Level Design Constraints, an extension to the SDC commands available in the solution.

These constraints describe the cell interface, thus enabling accurate linting of the rest of the design while ignoring the internal structure of the IP. This approach not only improves the accuracy of linting results, but also speeds up analysis by replacing IPs with robust models optimized for linting.

The Block Level Design Constraints extension in ALINT-PRO-CDC covers these design unit types:

• Encrypted IP modules
• Non-synthesizable and behavioral descriptions
• Black boxes
• Custom synchronization cells

How to use Block Level Design Constraints Extension in ALINT-PRO-CDC

In order to use Block Level Constraints in ALINT-PRO-CDC, they must first be specified in the *.adc or *.sdc files and added to the project. Design constraints eventually influence the netlist, which is generated after the “Constrain” phase. However, unlike chip level design constraints, block level constraints are applied on the Parse phase and are saved in the library (see Figure 1). This allows specifying block level constraints in each project individually and then gathering them together on the “Constrain” phase.

Figure 1 - Design entry process in ALINT-PRO-CDC™

Block level constraints cover the following aspects of the cells:

• Define cell function: RAM, ROM, flip-flop, latch, etc.
• Define pin function: asynchronous/synchronous set/reset, enable, data pin, synchronizer input/output
• Define cell clocks, generated clocks and relations between them
• Define which pins are controlled by which clock

To fine tune a cell’s description, all constraints allow specifying expressions using generics to control the condition when a particular constraint is applied to the cell. It is even possible to specify design constraints which depend on the constant value, driving the input port of the cell.

The constraints mechanism is powerful enough to describe complicated cells, such as, PLLs, DCMs and all sorts of computational elements from FPGA vendor libraries.

For additional information about block level design constraints, please refer to the following:

Application Note: Using Block Level Constraints for Description of Non-Synthesizable Design Units in ALINT-PRO-CDC

About Aldec ALINT-PRO-CDC™

ALINT-PRO-CDC is a design verification solution focused on clock domain crossing analysis and handling of metastability issues in complex, modern multi-clock designs. The tool uncovers critical problems during the RTL Design and Functional Verification stages, significantly reducing time to market. ALINT-PRO-CDC is available in 32-bit and 64-bit versions that can run on Windows and Linux OS platforms support x86 and x86_64 CPU architectures.

For a free evaluation download or to learn more, visit www.aldec.com/products/alint-pro-cdc or contact Aldec Sales at +1-702-990-4400 or sales@aldec.com.