Aldec Design and Verification Blog Trending Articles Advanced Static Linting for FPGA Performance Optimization Scalable Cloud-based CI/CD HDL Verification Environment Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Advanced Static Linting for FPGA Performance Optimization How to Boost Design Speed and Efficiency Accelerate FPGA Design with Advanced Static Linting In modern high-speed FPGA design, raw performance isn’t enough. Engineers face increasing challenges in achieving higher clock frequencies, lower power consumption, and smaller silicon footprints... Tags:FPGA,Prototyping,FPGA Simulation,Design,Hardware,HDL,Linting,safety-critical,Simulation,STARC,Verification,Xilinx Like(0) Comments (0) Read more Scalable Cloud-based CI/CD HDL Verification Environment Enhance Your Verification Workflow with Azure, VUnit, and Riviera-PRO Verification is the cornerstone of digital design, ensuring high reliability and functional correctness of FPGA and SoC designs. By integrating Azure’s scalable cloud computing, the open-source unit testing capabilities of VUnit, and the high-performance simulation engine of Riviera-PRO,... Tags:Aceleration,Functional Verification,HDL,Riviera-PRO,Simulation,Verification,VHDL Like(0) Comments (0) Read more Navigating VUnit: A Practical Guide to Modifying Testing Approaches In the two previous blogs, we introduced you to the world of VUnit, guided you through creating a project from scratch, and demonstrated how to run multi-threaded unit testing of multiple independent tests.... Tags:Aceleration,Functional Verification,HDL,Riviera-PRO,Simulation,Verification,VHDL Like(0) Comments (0) Read more FPGA Design Verification in a Nutshell FPGA Design Verification (Planning) in a Nutshell Before wading into this topic, I’d like to state why I felt compelled to write about FPGA design verification. I recently presented a very well attended three-part webinar series, during which many attendees asked for book recommendations.... Tags:ASIC,Coverage,Design,Functional Verification,Debugging,Documentation,Digital,SoC,Verification,Verilog,VHDL Like(0) Comments (0) Read more The Convergence of Emulation and Prototyping During the development of a system on chip (SoC), hardware emulation and FPGA prototyping play distinct and essential roles. ● Emulation is used to verify that a design meets its functional requirements, where the verification is performed by emulating the hardware and simulating (using a testbench) the environment in which it must perform.... Tags:ARM,ASIC,Emulation,FPGA,SoC,Validation,Verification Like(3) Comments (0) Read more Linting RISC-V designs with ALINT-PRO As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions, and their flexibility, creates a problem when choosing the most reliable and robust solution from a number of contenders.... Tags:ASIC,FPGA,HDL,Verification,Verilog,Design,Digital,IP,Linting,SoC,SystemVerilog Like(2) Comments (0) Read more Connecting Emulated Design to External PCI Express Device These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it. Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation... Tags:ARM,ASIC,Emulation,FPGA,SoC,Validation,Verification Like(2) Comments (0) Read more ARM-based SoC Co-Emulation using Zynq Boards Ready-to-use Co-Emulation Platform Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome?... Tags:ARM,ASIC,Emulation,FPGA,SoC,Validation,Verification,Zynq Like(1) Comments (0) Read more When is robustness verification for DO-254 projects complete? Understandably, hardware designed for an aircraft, or indeed any safety critical application, must be robust. I also believe that all engineers wish to verify their designs as thoroughly as possible, anyway. However, there are limiting factors; most notably the high complexity of most designs. Since we are unable to discover and verify the design against all abnormal conditions, the main question is: when is robustness verification truly complete?... Tags:FPGA,safety-critical,Verification Like(6) Comments (0) Read more HW/SW Co-Verification Environment for Hybrid Systems Using QEMU SoC Verification Never Been Easier At the beginning of September, Aldec announced the new version of HES.Proto-AXI software, our host to FPGA bridge solution. This tool supports QEMU for Co-Verification purposes which is considered as one of the main features.... Tags:ARM,Co-simulation,SoC,Verification Like(2) Comments (0) Read more
